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| 型號： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 20/97頁 |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KCW |
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AMD
P R E L I M I N A R Y
20
SUPERNET 3
RS 5:0
Receive Status pins (outputs)
An additional receive status pin has been added to
provide more receive information. The encoding of the
status pins is fully backward compatible with the
SUPERNET 2 chipset. The enhanced encoding is
enabled by setting the MENRS bit in the mode register 3
(MDREG3). The encoding of the RS pins is shown on
the following table.
RS5
RS4
RS3
RS2
RS1
RS0
Indicated Status
0
X
X
X
X
X
As in SUPERNET 2 FORMAC Plus
1
0
0
0
0
0
Reserved
1
0
X
0
0
1
Starting Delimiter and non-data
symbol received
1
0
0
0
1
0
OSM mode: Stripping frame
1
0
0
0
1
1
Reserved
1
0
0
1
0
0
Reserved
1
0
0
1
0
1
Frame Abort
1
0
0
1
1
0
Frame Flush
1
0
0
1
1
1
Reserved
through
1
1
1
1
1
1
Reserved
QCTRL 2:0
Queue Control pins (outputs)
The encoding of the QCTRL pins is as follows:
QCTRL2 QCTRL1 QCTRL0 Indicated Status
0
0
0
(1) Quiescent.
(2) Space remains for more
data while loading a
transmit queue
Unloading transmit frame
from Synchronous Queue
Unloading transmit frame
from Asynchronous Queue 0
Unloading transmit frame
from Asynchronous Queue 1
Reserved
Current transmit frame
Underrun
Current transmit queue full
Current transmit queue
almost full
0
0
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
1
Slower Buffer Memory Interface
The buffer memory interface has been modified ena-
bling slower SRAMs (35 ns) to be used as buffer
memory. This reduces the system cost. The interface is
fully backward compatible with the SUPERNET 2 buffer
memory interface.
Clocking
LSCLK
Local Symbol Clock pin (input)
The LSCLK is a 25 MHz clock. It is used by the
PLC-S and PDX cores.
BCLK
Byte Clock pin (input)
The BCLK is a 12.5 MHz clock. It is used by the PLC-S
and the MAC cores.
BMCLK
Buffer Memory Clock pin (input)
The BMCLK is the clock signal that the MAC core uses
for generating the signals to the buffer memory. BMCLK
is driven with either a 12.5 or 25 MHz clock signal. If
12.5 MHz operation is desired, then this pin must be tied
to BCLK pin. If 25 MHz operation is desired, then this pin
must be tied to LSCLK pin.
A, C Indicators
The setting of the A, C indicators has been modified to
allow the indicator setting to be selectable in any of the
modes: online, online special mode, or external loop-
back. The A, C indicators can be set as normal, MSC
method, or not modified at all. The modified setting of
the A, C indicators can be selected by setting the
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