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參數(shù)資料
| 型號： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 2/97頁 |
| 文件大小： | 358K |
| 代理商： | AM79C850KCW |
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AMD
P R E L I M I N A R Y
2
SUPERNET 3
configurations with an external physical layer
controller.
I
SUPERNET 3 has a Test Access Port and
Boundary Scan Architecture, IEEE1149.1.
I
SUPERNET 3 provides Built-in Self Test (BIST)
features for the Address Filter, and PLC-S.
I
All registers are readable and writable by the Node
Processor. All reserved bits shall be read back as
zero except where noted.
I
The Receive Status (RS) pins are expanded from
5 to 6 pins to support enhanced status reporting.
I
The Transmit Status (XS) pins are expanded from
3 to 4 pins to support enhanced status reporting.
I
Enhanced frame reception is possible by splitting
the receive queue.
I
Modified TAG Mode of operation for easy
conversion from NON-TAG SUPERNET 2 to
SUPERNET 3.
I
All SUPERNET 3 registers will be initialized with a
default value on reset.
I
The A, C indicator setting has been modified. It is
now possible to control the setting of the A, C
indicators independent of the mode of operation
(online, online special mode, and external
loopback mode).
I
Maskable ‘vectored-interrupts’ are provided. It is
now possible to detect the event causing the
interrupt in the SUPERNET 3 in two cycles by
reading the vector register which gives the vector
of the status register followed by a read of the
appropriate status register.
I
An additional mode register (MDREG3) is
provided. Setting the bits in this mode register
enables the additional SUPERNET 3 features.
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