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參數(shù)資料
| 型號： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 18/97頁 |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KCW |
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AMD
P R E L I M I N A R Y
18
SUPERNET 3
fashion to the
XDAMAT
pin. This input is used in
conjunction with the
XDAMAT
pin as follows:
Match
Action
XDA_XACT
and
XDAMAT
A, C indicators set
and frame copied*.
Invalid combination.
Ignored by MAC.
A, C indicators not set
and frame copied.
No action.
XDA_XACT
and XDAMAT
XDA_XACT and
XDAMAT
XDA_XACT and XDAMAT
* Frame is copied if valid frame or if in promiscuous or
limited promiscuous mode. In OSM, the A, C indicators
are set according to the OSM rules if bits 4, 5
(MEIND0,1) are set.
The
XDA_XACT
pin which is generated by the external
AF is logically ORed with the “af_dax” output signal
generated by the internal AF logic. This pin is enabled
only if the MENXACT bit in the mode register 3 is set.
This pin should be tied high when external address
detection (such as an external AF) is not used.
XSAMAT
External Source Address Match (TTL input, active
low)
This input provides a means for additional source-ad-
dress detection external to the SUPERNET 3. This pin
should be tied high when external source-address de-
tection is not used. This input should remain asserted for
at least one BCLK cycle, and must be deasserted for at
least one BCLK cycle before a subsequent external des-
tination address match is recognized.
The
XSAMAT
pin which is generated by the external AF
is logically ORed with the “af_sa” output signal gener-
ated by the internal AF logic. This pin should be tied high
when external address detection (such as an external
AF) is not used.
XSA_XACT
External Source Address Exact Match (TTL input,
active low)
This input indicates whether the external source ad-
dress match was exact (low) or inexact (high). This input
should remain asserted for at least one BCLK cycle, and
must be deasserted for at least one BCLK cycle before a
subsequent external source address match is recog-
nized. It must be asserted and deasserted in an identical
fashion to the
XSAMAT
pin. This input is used in con-
junction with the
XSAMAT
pin as follows:
Match
Action
XSA_XACT
and
XSAMAT
XSA_XACT
and XSAMAT
Frame stripped.
Invalid combination.
Ignored by MAC.
Frame not stripped.
No action.
XSA_XACT and
XSAMAT
XSA_XACT and XSAMAT
The
XSA_XACT
pin which is generated by the external
AF is logically ORed with the “af_sax” output signal
generated by the internal AF logic. This pin is enabled
only if the MENXACT bit in the mode register 3 is set.
This pin should be tied high when external address
detection (such as an external AF) is not used.
RST
Reset (TTL input)
The
RST
signal (active low) is an asynchronous input
that initializes the internal SUPERNET 3 state machines
and registers. Once
RST
is asserted low, it must remain
asserted for at least twenty BCLK cycles. When it is
deasserted the SUPERNET 3 is ready to begin normal
operation only after 750 LSCLK cycles. The 750 LSCLK
cycles are needed for calibration of the PDX core.
Assertion and deassertion are asynchronous. A warm
reset (assertion of
RST
after the device is in operation)
will cause device outputs to be unpredictable until the
device is initialized.
Testability Interface (5 Pins)
TCK
Test Clock In (TTL input)
TCK provides the clock for the test logic. Any stored-
state devices contained in the test logic must retain their
state indefinitely if the signal applied to TCK is held high
or low.
TMS
Test Mode Select In (TTL input, Synchronous to
TCK)
The test mode select input directs the operation of the
generation of the TAP controller. The state of the TMS
signal is sampled on the rising edge of TCK. If for some
reason TMS is not driven externally, the TAP controller
should behave as if this signal were driven with a logic 1
(internal pull-up).
TDI
Test Data In (TTL input, Synchronous to TCK)
This pin provides for the application of serial instructions
and data. The state of this signal is sampled on the rising
edge of TCK. If for some reason TDI is not driven
externally, the test logic should behave as if a logic 1
were applied to this signal (internal pull-up).
TDO
Test Data Output (TTL Output, 3-state,
Synchronous to TCK)
This pin provides the serial output for instructions
and data from the test logic. No inversion of data is
allowed between TDI and TDO during shift operations.
The state of TDO changes on the falling edge of TCK.
TDO is in the high impedance state except during
shifting operations.
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