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參數(shù)資料
| 型號： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 92/98頁 |
| 文件大?。?/td> | 851K |
| 代理商： | AK4343 |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 92 -
Stereo Line Output
FS3-0 bits
(Addr:05H, D5&D2-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMLO bit
(Addr:00H, D3)
1,111
0,000
18H
28H
LOUT pin
ROUT pin
(1)
(4)
(5)
(2)
DACL bit
(Addr:02H, D4)
(10)
Normal Output
(7)
LOPS bit
(Addr:03H, D6)
(6)
>300 ms
(8)
(9)
>300 ms
(11)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
91H
(3)
PMMIN bit
(Addr:00H, D5)
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume:
8dB
LOVL=MINL bits = “0”
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:10H
(4) Addr:0AH&0DH, Data:28H
(5) Addr:03H, Data:40H
(6) Addr:00H, Data:6CH
(7) Addr:03H, Data:00H
Playback
(8) Addr:03H, Data:40H
(9) Addr:00H, Data:40H
(10) Addr:02H, Data:00H
(11) Addr:03H, Data:00H
(3) Addr:09H&0CH, Data:91H
Figure 82. Stereo Lineout Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4343 is PLL mode, DAC and Stereo Line-Amp
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “DAC
Stereo Line Amp”: DACL bit = “0”
“1”
(3) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(4) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0”
“1”
(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “0”
→
“1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The
initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital
data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input
data after the initialization cycle is complete. When ALC bit is “1”, ALC is disable (ALC gain is set by
AVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle,
ALC operation starts from the gain set by AVL/R7-0 bits.
LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max)
at C=1
μ
F and AVDD=3.3V.
(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
“0”
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0”
“1”
(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “1”
→
“0”
LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1
μ
F and AVDD=3.3V.
(10) Disable the path of “DAC
Stereo Line-Amp”: DACL bit = “1”
“0”
(11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
“0”
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
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