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參數(shù)資料
| 型號： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 57/98頁 |
| 文件大小： | 851K |
| 代理商： | AK4343 |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 57 -
Headphone Output
Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage at
VBAT bit = “0”. The load resistance is 16
(min). HPG bit selects the output voltage (see Table 49).
HPG bit
0
Output Voltage [Vpp]
0.6 x AVDD
Table 49. Headphone-Amp Output Voltage
When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to
“L” (HVSS). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at VBAT bit = “0”. A capacitor between
the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage
and the capacitor at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0
μ
F, HVDD=3.3V:
Rise/fall time constant:
τ
= 100ms(typ), 250ms(max)
Time until the common goes to HVSS when HPMTN bit = “1”
“0”: 500ms(max)
When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go
to “L” (HVSS).
PMHPL bit,
PMHPR bit
1
0.91 x AVDD
(1) (2)
(4)
(3)
HPMTN bit
HPL pin,
HPR pin
Figure 52. Power-up/Power-down Timing for Headphone-Amp
(1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still HVSS.
(2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising.
(3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling.
(4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are HVSS. If the power supply is switched
off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs.
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