參數(shù)資料
型號： AK4343
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Stereo DAC with HP/RCV/SPK-AMP
中文描述： 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷
文件頁數(shù)： 10/98頁
文件大?。?/td> 851K
代理商： AK4343
ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 10 -
Parameter
Speaker-Amp Characteristics:
DAC
→
SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, R
L
=8
, BTL,
HVDD=3.3V; unless otherwise specified.
Output Voltage (Note 17)
SPKG1-0 bits = “00”,
0.5dBFS (Po=150mW)
SPKG1-0 bits = “01”,
0.5dBFS (Po=240mW)
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
Line Input
SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”,
1.5dBV Input (Po=1.2W)
S/(N+D)
SPKG1-0 bits = “00”,
0.5dBFS (Po=150mW)
SPKG1-0 bits = “01”,
0.5dBFS (Po=240mW)
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
Line Input
SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”,
1.5dBV Input (Po=1.2W)
S/N (A-weighted)
Load Resistance
Load Capacitance
Speaker-Amp Characteristics:
DAC
→
SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, C
L
=3
μ
F, R
series
=10
x
2, BTL, HVDD=5.0V; unless otherwise specified.
Output Voltage
SPKG1-0 bits = “10”, 0dBFS
(Note 17) SPKG1-0 bits = “11”, 0dBFS
S/(N+D)
SPKG1-0 bits = “10”, 0dBFS
(Note 18) SPKG1-0 bits = “11”, 0dBFS
S/N
(A-weighted)
Load Resistance (Note 19)
Load Capacitance (Note 19)
Mono Input:
MIN pin (AIN3 bit = “0”; External Input Resistance=20k
)
Maximum Input Voltage (Note 20)
Gain (Note 21)
MIN
LOUT/ROUT
LOVL bit = “0”
LOVL bit = “1”
MIN
HPL/HPR
HPG bit = “0”
24.5
HPG bit = “1”
MIN
SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
0.07
ALC bit = “0”, SPKG1-0 bits = “01”
ALC bit = “0”, SPKG1-0 bits = “10”
ALC bit = “0”, SPKG1-0 bits = “11”
ALC bit = “1”, SPKG1-0 bits = “00”
ALC bit = “1”, SPKG1-0 bits = “01”
ALC bit = “1”, SPKG1-0 bits = “10”
ALC bit = “1”, SPKG1-0 bits = “11”
Note 17. Output voltage is proportional to AVDD voltage.
Vout = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x AVDD(typ)@SPKG1-0 bits = “01”, 2.05 x
AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0 bits = “11” at Full-differential output.
Note 18. In case of measuring at SPP and SPN pins.
Note 19. Load impedance is total impedance of series resistance (R
series
) and piezo speaker impedance at 1kHz in Figure
58. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10
or more series resistors
should be connected at both SPP and SPN pins, respectively.
Note 20. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin
/ 20k
(typ).
Note 21. The gain is in inverse proportion to external input resistance.
min
typ
max
Units
-
3.11
3.92
3.92
-
Vpp
Vpp
Vpp
3.13
3.13
4.71
4.71
-
2.83
-
Vrms
-
60
50
30
-
-
-
dB
dB
dB
20
20
-
20
-
dB
80
8
-
90
-
-
-
-
dB
pF
30
-
6.75
8.50
60
50
90
-
-
-
Vpp
Vpp
dB
dB
dB
μ
F
6.80
-
40
80
50
-
10.20
-
-
-
-
3
-
1.98
-
Vpp
4.5
-
0
+2
20
16.4
+4.43
+6.43
+10.65
+12.65
+6.43
+8.43
+12.65
+14.65
+4.5
-
15.5
-
+8.93
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
-
-
-
-
-
-
-
-
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