參數(shù)資料
型號: AK4343
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Stereo DAC with HP/RCV/SPK-AMP
中文描述: 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷
文件頁數(shù): 81/98頁
文件大?。?/td> 851K
代理商: AK4343
ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 81 -
SYSTEM DESIGN
Figure 72 and Figure 73 shows the system connection diagram for the AK4343. An evaluation board [AKD4343] is
available which demonstrates the optimum layout, power supply arrangements and measurement results.
MUTET
ROUT
LOUT
MIN
RIN2
LIN2
LIN1
RIN1
H
H
H
H
S
S
M
M
N
V
A
A
V
I
P
C
DVSS
DVDD
BICK
LRCK
NC
SDTI
CDTI
CCLK
AK4343EN
Top View
25
26
27
28
29
30
31
32
2
2
2
1
16
15
14
13
12
11
10
9
2
2
1
1
1
2
3
4
5
6
7
8
Line In
1u
0
2
0
R
6
4
6
4
10
0.22u
10
0.22u
Power Supply
2.6
3.6V
0
0.1u
1
DSP
μ
P
Line Out
Headphone
Speaker
Mono In
Cp
10u
Analog Ground
Digital Ground
1u
1u
200
200
2
2
ZD2
ZD1
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2:
10
ZD1, ZD2: Required
R
R
Notes:
- AVSS, DVSS and HVSS of the AK4343 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When the AK4343 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4343 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 5.
- When piezo speaker is used, 2.6
5.25V power should be supplied to HVDD and 10
or more series resistors
should be connected to both SPP and SPN pins, respectively.
- When the AK4343 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100k
around pull-up resistor should be connected to LRCK and BICK pins of the AK4343.
Figure 72. Typical Connection Diagram (AIN3 bit = “0”, Line Input)
相關(guān)PDF資料
PDF描述
AK4343EN Stereo DAC with HP/RCV/SPK-AMP
AK4345 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
AK4345ET 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
AK4346 3.3V 192kHz 24-Bit 6-Channel DAC
AK4346EF 3.3V 192kHz 24-Bit 6-Channel DAC
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