- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385090 > AK4343 (Asahi Kasei Microsystems Co.,Ltd) Stereo DAC with HP/RCV/SPK-AMP PDF資料下載
參數(shù)資料
| 型號(hào)： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 24/98頁 |
| 文件大?。?/td> | 851K |
| 代理商： | AK4343 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 24 -
OPERATION OVERVIEW
System Clock
There are the following four clock modes to interface with external devices (see Table 2 and Table 3).
Mode
PMPLL bit
PLL Master Mode (Note 37)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
EXT Master Mode
Note 37. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 2. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
M/S bit
1
PLL3-0 bits
See Table 5
Figure
Figure 18
1
1
0
See Table 5
Figure 19
1
0
See Table 5
Figure 20
Figure 21
Figure 22
Figure 23
0
0
0
1
x
x
MCKO pin
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
MCKI pin
BICK pin
Output
(Selected by
BCKO bit)
LRCK pin
Selected by
PLL3-0 bits
Output
(1fs)
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
Selected by
PLL3-0 bits
Input
(
≥
32fs)
Input
(1fs)
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
GND
Input
(Selected by
PLL3-0 bits)
Input
(
≥
32fs)
Output
(Selected by
BCKO bit)
Input
(1fs)
EXT Slave Mode
0
“L”
Selected by
FS1-0 bits
Input
(1fs)
EXT Master Mode
0
“L”
Selected by
FS1-0 bits
Output
(1fs)
Table 3. Clock pins state in Clock Mode
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4343 is power-down mode (PDN pin = “L”) and exits reset state, the AK4343 is slave mode. After exiting reset state,
the AK4343 goes to master mode by changing M/S bit = “1”.
When the AK4343 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK4343 should be pulled-down or pulled-up by the resistor (about 100k
) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 4. Select Master/Slave Mode
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4343EN | Stereo DAC with HP/RCV/SPK-AMP |
| AK4345 | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
| AK4345ET | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
| AK4346 | 3.3V 192kHz 24-Bit 6-Channel DAC |
| AK4346EF | 3.3V 192kHz 24-Bit 6-Channel DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK434-3 | 功能描述:CABLE CENTRONICS F-F 3M RoHS:否 類別:電纜組件 >> D形，Centronics 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 配置:VHDCI 68 位置公型至公型 長度:10.00'（3.05m） 纜線類型:圓形 - 黑色 屏蔽:屏蔽 樣式:SCSI Ultra 2 |
| AK4343EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with HP/RCV/SPK-AMP |
| AK4343VNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK4343VNP-L |
| AK4344 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC |
| AK4344_10 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。