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參數(shù)資料
| 型號： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 89/98頁 |
| 文件大?。?/td> | 851K |
| 代理商： | AK4343 |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 89 -
Speaker-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMSPK bit
(Addr:00H, D4)
1,111
0,000
18H
28H
SPP pin
Normal Output
SPPSN bit
(Addr:02H, D7)
Hi-Z
Hi-Z
SPN pin
Normal Output
Hi-Z
Hi-Z
HVDD/2
HVDD/2
(1)
(9)
1
0
(7)
ALC bit
(Addr:07H, D5)
(10)
(11)
(14)
(12)
DACS bit
(Addr:02H, D5)
(13)
01
00
(3)
SPKG1-0 bits
(Addr:03H, D4-3)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
91H
(8)
(2)
(6)
ALC Control 1
(Addr:06H)
00H
3CH
(4)
ALC Control 2
(Addr:08H)
E1H
C1H
(5)
ALC Control 3
(Addr:0BH)
00H
00H
PMMIN bit
(Addr:00H, D5)
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Digital Volume:
8dB
ALC: Enable
(2) Addr:02H, Data:20H
(7) Addr:07H, Data:20H
(1) Addr:05H, Data:27H
(9) Addr:0AH & 0DH, Data:28H
(10) Addr:00H, Data:74H
(11) Addr:02H, Data:A0H
(12) Addr:02H, Data:20H
Playback
(13) Addr:02H, Data:00H
(14) Addr:00H, Data:40H
(3) Addr:03H, Data:08H
(8) Addr:09H & 0CH, Data:91H
(4) Addr:06H, Data:3CH
(5) Addr:08H, Data:E1H
(6) Addr:0BH, Data:00H
Figure 79. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4343 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC
SPK-Amp”: DACS bit = “0”
“1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00”
“01”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(8) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(9) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
(10) Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPK bits = “0”
→
“1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The
initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital
data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input
data after the initialization cycle is complete. When ALC bit is “1”, ALC is disable (ALC gain is set by
AVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by AVL/R7-0 bits.
(11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0”
→
“1”
(12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1”
→
“0”
(13) Disable the path of “DAC
SPK-Amp”: DACS bit = “1”
“0”
(14) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPK bits = “1”
→
“0”
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