參數資料
型號: AK4343
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Stereo DAC with HP/RCV/SPK-AMP
中文描述: 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷
文件頁數: 52/98頁
文件大?。?/td> 851K
代理商: AK4343
ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 52 -
Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10k
(min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down
to AVSS by 100k
(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be
pulled-down to AVSS by 20k
after AC coupled as Figure 42. Rise/Fall time is 300ms(max) at C=1
μ
F and
AVDD=3.3V. When PMLO=LOPS bits = “1”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
“DACL”
DAC
LOUT pin
ROUT pin
“LOVL”
Figure 41. Stereo Line Output
LOPS
PMLO
0
1
0
1
Table 45. Stereo Line Output Mode Select (x: Don’t care)
Mode
LOUT/ROUT pin
Pull-down to AVSS
Normal Operation
Fall down to AVSS
Rise up to VCOM
Default
Power-down
Normal Operation
Power-save
Power-save
0
1
LOVL
0
1
Gain
+0dB
+2dB
Output Voltage (typ)
0.6 x AVDD
0.757 x AVDD
Default
Table 46. Stereo Line Output Volume Setting
LOUT
ROUT
1
μ
F
220
20k
Figure 42. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
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