- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385090 > AK4343 (Asahi Kasei Microsystems Co.,Ltd) Stereo DAC with HP/RCV/SPK-AMP PDF資料下載
參數(shù)資料
| 型號： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 84/98頁 |
| 文件大小： | 851K |
| 代理商： | AK4343 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁當前第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 84 -
CONTROL SEQUENCE
Clock Set up
When DAC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
BICK pin
LRCK pin
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
40msec(max)
Output
(1)
(6)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
(2)
(3)
MCKI pin
(5)
(4)
Input
M/S bit
(Addr:01H, D3)
MCKO pin
Output
(8)
(7)
40msec(max)
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L”
“H”
(3)Addr:00H, Data:40H
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(4)Addr:01H, Data:0BH
MCKO, BICK and LRCK output
Figure 74. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L”
“H”
“L” time of 150ns or more is needed to reset the AK4343.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power UpVCOM: PMVCM bit = “0”
“1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4343 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4343EN | Stereo DAC with HP/RCV/SPK-AMP |
| AK4345 | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
| AK4345ET | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
| AK4346 | 3.3V 192kHz 24-Bit 6-Channel DAC |
| AK4346EF | 3.3V 192kHz 24-Bit 6-Channel DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK434-3 | 功能描述:CABLE CENTRONICS F-F 3M RoHS:否 類別:電纜組件 >> D形，Centronics 系列:- 標準包裝:1 系列:- 配置:VHDCI 68 位置公型至公型 長度:10.00'（3.05m） 纜線類型:圓形 - 黑色 屏蔽:屏蔽 樣式:SCSI Ultra 2 |
| AK4343EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with HP/RCV/SPK-AMP |
| AK4343VNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK4343VNP-L |
| AK4344 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC |
| AK4344_10 | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC |
發(fā)布緊急采購，3分鐘左右您將得到回復。