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參數(shù)資料
| 型號(hào)： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車(chē)/胰腎聯(lián)合移植腺苷 |
| 文件頁(yè)數(shù)： | 86/98頁(yè) |
| 文件大?。?/td> | 851K |
| 代理商： | AK4343 |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 86 -
3. PLL Slave Mode (MCKI pin)
BICK pin
LRCK pin
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
(1)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
(2)
(3)
MCKI pin
(5)
(4)
Input
MCKO pin
Output
(6)
(7)
40msec(max)
(8)
Input
Example:
Audio I/F Format: MSB justified
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L”
“H”
(3)Addr:00H, Data:40H
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
(4)Addr:01H, Data:03H
MCKO output start
BICK and LRCK input start
Figure 76. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L”
“H”
“L” time of 150ns or more is needed to reset the AK4343.
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
“1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
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