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參數(shù)資料
| 型號： | AK4343 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Stereo DAC with HP/RCV/SPK-AMP |
| 中文描述： | 立體聲DAC惠普/垃圾車/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 91/98頁 |
| 文件大小： | 851K |
| 代理商： | AK4343 |
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ASAHI KASEI
[AK4343]
MS0478-E-01
2006/10
- 91 -
Headphone-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMHPL/R bits
(Addr:01H, D5-4)
HPMTN bit
(Addr:01H, D6)
HPL/R pins
1,111
0,000
18H
28H
Normal Output
(1)
BST1-0 bits
(Addr:0EH, D3-2)
00
10
00
(3)
(5)
(12)
PMDAC bit
(Addr:00H, D2)
(6)
(11)
(7)
(9)
(8)
(10)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
91H
(4)
PMMIN bit
(Addr:00H, D5)
DACH bit
(Addr:0FH, D0)
(2)
(13)
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Bass Boost Level : Middle
8dB
(1) Addr:05H, Data:27H
(2) Addr:0FH, Data:09H
(4) Addr:09H&0CH, Data:91H
(5) Addr:0AH&0DH, Data:28H
(6) Addr:00H, Data:64H
(7) Addr:01H, Data:39H
(8) Addr:01H, Data:79H
Playback
(9) Addr:01H, Data:39H
(10) Addr:01H, Data:09H
(11) Addr:00H, Data:40H
(3) Addr:0EH, Data:19H
(12) Addr:0EH, Data:11H
(13) Addr:0FH, Data:08H
Figure 81. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4343 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC
→
HP-Amp”: DACH bit = “0”
→
“1”
(3) Set up the low frequency boost level (BST1-0 bits)
(4) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0”
→
“1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The
initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital
data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input
data after the initialization cycle is complete. When ALC bit is “1”, ALC is disable (ALC gain is set by
AVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle,
ALC operation starts from the gain set by AVL/R7-0 bits.
(7) Power up headphone-amp: PMHPL = PMHPR bits = “0”
→
“1”
Output voltage of headphone-amp is still HVSS.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0”
→
“1”
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0
μ
F, the time constant is
τ
r
= 100ms(typ), 250ms(max).
(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1”
→
“0”
The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0
μ
F, the time constant is
τ
f
= 100ms(typ), 250ms(max).
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to
GND, the pop noise occurs. It takes twice of
τ
f
that the common voltage goes to GND.
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1”
→
“0”
(11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1”
→
“0”
(12) Off the bass boost: BST1-0 bits = “00”
(13) Disable the path of “DAC
→
HP-Amp”: DACH bit = “1”
→
“0”
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