參數(shù)資料
型號(hào): ADV7321KSTZ
廠商: Analog Devices Inc
文件頁數(shù): 77/88頁
文件大?。?/td> 0K
描述: IC VID ENC 6-12BIT DAC'S 64LQFP
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: EVD,DVD,SD/PS/HDTV
電壓 - 電源,模擬: 2.5V
電壓 - 電源,數(shù)字: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
ADV7320/ADV7321
Rev. A | Page 79 of 88
MODE 2—MASTER OPTION
(TIMING REGISTER 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7320/ADV7321 can generate horizontal
and vertical sync signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field.
A VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7320/ADV7321 automatically blank
all normally blank lines as per CCIR-624. HSYNC, BLANK,
and VSYNC are output on S_HSYNC, S_BLANK, and
S_VSYNC, respectively.
Cb
Y
05067-118
PIXEL
DATA
HSYNC
BLANK
VSYNC
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
Y
Cr
Figure 118. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave
Cb
PIXEL
DATA
HSYNC
BLANK
VSYNC
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
PAL = 864
× CLOCK/2
NTSC = 858
× CLOCK/2
Cb
Y
Cr
05067-119
Figure 119. SD Timing Mode 2 Odd-to-Even Field Transition
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