參數(shù)資料
型號: ADV7321KSTZ
廠商: Analog Devices Inc
文件頁數(shù): 7/88頁
文件大?。?/td> 0K
描述: IC VID ENC 6-12BIT DAC'S 64LQFP
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: EVD,DVD,SD/PS/HDTV
電壓 - 電源,模擬: 2.5V
電壓 - 電源,數(shù)字: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
ADV7320/ADV7321
Rev. A | Page 15 of 88
Y9–Y0
Cb
Y
Cr
Y
b
a
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
P_HSYNC
P_VSYNC
P_BLANK
05067-016
Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram
Cb
Y
Cr
Y
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
S9–S0/Y9–Y0*
*SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21.
S_HSYNC
S_VSYNC
S_BLANK
05067-017
Figure 17. SD Timing Input for Timing Mode 1
t3
t1
t6
t2
t7
t5
SDA
SCLK
t3
t4
t8
05067-018
t1 = SCLOCK HIGH PULSE WIDTH
t2 = SCLOCK LOW PULSE WIDTH
t3 = HOLD TIME (START CONDITION)
t4 = SETUP TIME (START CONDITION)
t5 = DATA SETUP TIME
t6 = SDATA, SCLOCK RISE TIME
t7 = SDATA, SCLOCK FALL TIME
t8 = SETUP TIME (STOP CONDITION)
Figure 18. MPU Port Timing Diagram
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