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參數(shù)資料
| 型號(hào)： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 70/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 72 of 88
The register settings in Table 41 are used to generate an SD NTSC
CVBS output on DAC A, S-video on DACs B and C, and YPrPb
on DACs D, E, and F. Upon power-up, the subcarrier registers
are programmed with the appropriate values for NTSC. All
other registers are set as normal/default.
Table 41. NTSC Test Pattern Register Writes
Subaddress
Register Setting
0x00
0xFC
0x40
0x10
0x42
0x40
0x44
0x40 (internal test pattern on)
0x4A
0x08
For PAL CVBS output on DAC A, the same settings are used,
except Subaddress 0x40 is programmed to 0x11 and the FSC
registers are programmed as shown in Table 42.
Table 42. PAL FSC Register Writes
Subaddress
Description
Register Setting
0x4C
FSC0
0xCB
0x4D
FSC1
0x8A
0x4E
FSC2
0x09
0x4F
FSC3
0x2A
Note that when programming the FSC registers, the user must
write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full
FSC value is only accepted after the FSC3 write is complete.
The register settings in Table 43 are used to generate a 525p
hatch pattern on DAC D, E, and F. All other registers are set as
normal/default.
Table 43. 525p Test Pattern Register Writes
Subaddress
Register Setting
Ox00
0xFC
0x01
0x10
0x00
0x11
0x05
0x16
0xA0
0x17
0x80
0x18
0x80
For 625p hatch pattern on DAC D, the same register settings are
used except Subaddress 0x10 = 0x18.
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