參數資料
| 型號： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 40/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 45 of 88
RESET SEQUENCE
A reset is activated with a high-to-low transition on the RESET
pin (Pin 33) according to the timing specifications, and the
ADV7320/ADV7321 revert to the default output configuration.
Figure 63 illustrates the RESET timing sequence.
SD VCR FF/RW SYNC
[Subaddress 0x42, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit [Subaddress 0x42,
Bit 5] can be used for nonstandard input video, that is, in fast
forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields are reached; in rewind mode, this sync
signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals because one signal is generated by
the incoming video and another is generated when the internal
lines/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled, the line/field
counters are updated according to the incoming VSYNC signal,
and the analog output matches the incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
RESET
DIGITAL TIMING
DACs
A, B, C
PIXEL DATA
VALID
05067-039
Figure 63. RESET Timing Sequence
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相關代理商/技術參數 |
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