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參數(shù)資料
| 型號： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/88頁 |
| 文件大小： | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 34 of 88
Table 17. Registers 0x4A to 0x58
SR7–
SR0
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset
Value
0x4A
SD Slave/Master Mode
0
Slave mode.
0x08
SD Timing
Register 0
1
Master mode.
SD Timing Mode
0
Mode 0.
0
1
Mode 1.
1
0
Mode 2.
1
Mode 3.
SD BLANK Input
0
Enabled.
1
Disabled.
SD Luma Delay
0
No delay.
0
1
2 clock cycles.
1
0
4 clock cycles.
1
6 clock cycles.
SD Min. Luma Value
0
40 IRE.
1
7.5 IRE.
SD Timing Reset
x
0
A low-high-low transition resets
the internal SD timing counters.
0x4B
SD HSYNC Width
0
Ta = 1 clock cycle.
0x00
SD Timing
Register 1
0
1
Ta = 4 clock cycles.
1
0
Ta = 16 clock cycles.
1
Ta = 128 clock cycles.
0
Tb = 0 clock cycle.
SD HSYNC to VSYNC
Delay
0
1
Tb = 4 clock cycles.
1
0
Tb = 8 clock cycles.
1
Tb = 18 clock cycles.
x
0
Tc = Tb.
SD HSYNC to VSYNC
Rising Edge Delay
(Mode 1 Only)
x
1
Tc = Tb + 32 μs.
0
1 clock cycle.
VSYNC Width
(Mode 2 Only)
0
1
4 clock cycles.
1
0
16 clock cycles.
1
128 clock cycles.
0
0 clock cycles.
HSYNC to Pixel
Data Adjust
0
1
1 clock cycle.
1
0
2 clock cycles.
1
3 clock cycles.
0x4C
x
Subcarrier Frequency Bits 7 to 0.
0x4D
SD FSC Register 1
x
Subcarrier Frequency Bits 15 to 8.
0x7C
0x4E
SD FSC Register 2
x
Subcarrier Frequency Bits 23 to 16.
0xF0
0x4F
SD FSC Register 3
x
Subcarrier Frequency Bits 31 to 24.
0x21
0x50
SD FSC Phase
x
Subcarrier Phase Bits 9 to 2.
0x00
0x51
SD Closed
Captioning
Extended Data on
Even Fields
x
Extended Data Bits 7 to 0.
0x00
0x52
SD Closed
Captioning
Extended Data on
Even Fields
x
Extended Data Bits 15 to 8.
0x00
0x53
SD Closed
Captioning
Data on Odd Fields
x
Data Bits 7 to 0.
0x00
0x54
SD Closed
Captioning
Data on Odd Fields
x
Data Bits 15 to 8.
0x00
0x55
SD Pedestal
Register 0
Pedestal on Odd Fields
17
16
15
14
13
12
11
10
Setting any of these bits to 1
disables pedestal on the line num-
ber indicated by the bit settings.
0x00
0x56
SD Pedestal
Register 1
Pedestal on Odd Fields
25
24
23
22
21
20
19
18
0x00
0x57
SD Pedestal
Register 2
Pedestal on Even Fields
17
16
15
14
13
12
11
10
0x00
0x58
SD Pedestal
Register 3
Pedestal on Even Fields
25
24
23
22
21
20
19
18
0x00
1 For precise NTSC FSC, this register should be programmed to 0x1F.
LINE 313
LINE 314
LINE 1
tB
tA
tC
05067-024
HSYNC
VSYNC
Figure 48. Timing Register 1 in PAL Mode
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