參數(shù)資料
型號(hào)： ADV7321KSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/88頁(yè)
文件大?。?/td> 0K
描述： IC VID ENC 6-12BIT DAC'S 64LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： EVD，DVD，SD/PS/HDTV
電壓 - 電源，模擬： 2.5V
電壓 - 電源，數(shù)字： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
ADV7320/ADV7321
Rev. A | Page 39 of 88
The 8- or 10-bit SD data must be compliant with ITU-R
BT.601/656 in 4:2:2 format. SD data is input on Pins S9 to S0,
with S0 being the LSB. Using 8-bit input format, the data is
input on Pins S9 to S2. The clock input for SD must be input on
CLKIN_A, and the clock input for HD must be input on
CLKIN_B. Synchronization signals are optional. SD syncs are
input on Pins S_VSYNC, S_HSYNC, and S_BLANK. HD syncs
are input on Pins P_VSYNC, P_HSYNC, and P_BLANK.
CLKIN_A
CLKIN_B
MPEG2
DECODER
3
27MHz
10
YCrCb
INTERLACED TO
PROGRESSIVE
10
CrCb
10
Y
3
27MHz
S[9:0]
C[9:0]
Y[9:0]
ADV7320/
ADV7321
05067-027
S_VSYNC,
S_HSYNC,
S_BLANK
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 51. Simultaneous SD and PS Input
CLKIN_A
CLKIN_B
SDTV
DECODER
3
27MHz
10
YCrCb
10
CrCb
10
Y
3
74.25MHz
1080i
OR
720p
OR
1035i
S[9:0]
C[9:0]
Y[9:0]
ADV7320/
ADV7321
HDTV
DECODER
05067-028
S_VSYNC,
S_HSYNC,
S_BLANK
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 52. Simultaneous SD and HD Input
In simultaneous SD/HD input mode, if the two clock phases
differ by less than 9.25 ns or by more than 27.75 ns, the clock
align bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
clock align bit must be set because the phase difference between
both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
05067-029
tDELAY < 9.25ns OR
tDELAY > 27.75ns
Figure 53. Clock Phase with Two Input Clocks
PS AT 27 MHZ (DUAL EDGE) OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively
YCrCb PS data can be input at 27 MHz or 54 MHz. The input
data is interleaved onto a single 8-/10-bit bus and is input on
Pins Y9 to Y0. When a 27 MHz clock is supplied, the data is
clocked upon the rising and falling edges of the input clock, and
the clock edge bit [Address 0x01, Bit 1] must be set accordingly.
Table 22 provides an overview of all possible input
configurations. Figure 54, Figure 55, and Figure 56 show the
possible conditions: Cb data on the rising edge, and Y data on
the rising edge.
3FF
00
XY
Y0
Y1
Cr0
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Y9–Y0
Cb0
05067-030
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
3FF
00
XY
Cb0
Cr0
Y1
CLKIN_B
Y9–Y0
Y0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
05067-031
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
PIXEL INPUT
DATA
3FF
00
XY
Cb0
Y0
Y1
Cr0
CLKIN_B
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
05067-032
Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
MPEG2
DECODER
CLKIN_A
Y[9:0]
INTERLACED
TO
PROGRESSIVE
YCrCb
10
3
27MHz OR 54MHz
YCrCb
ADV7320/
ADV7321
P_VSYNC,
P_HSYNC,
P_BLANK
05067-033
Figure 57. 10-Bit PS at 27 MHz or 54 MHz
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