參數(shù)資料
型號： ADV7321KSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 37/88頁
文件大?。?/td> 0K
描述： IC VID ENC 6-12BIT DAC'S 64LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： EVD，DVD，SD/PS/HDTV
電壓 - 電源，模擬： 2.5V
電壓 - 電源，數(shù)字： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
ADV7320/ADV7321
Rev. A | Page 42 of 88
HD ASYNC TIMING MODE
[Subaddress 0x10, Bits 3 and 2]
For any input data that does not conform to the standards
selectable in input mode (Subaddress 0x10) asynchronous
timing mode can be used to interface to the ADV7320/ADV7321.
Timing control signals for HSYNC, VSYNC, and BLANK must
be programmed by the user. Macrovision and programmable
oversampling rates are not available in async timing mode.
In async mode, the PLL must be turned off [Subaddress 0x00,
Bit 1 = 1]. Register 0x10 should be programmed to 0x01.
Figure 58 and Figure 59 show examples of how to program the
ADV7320/ADV7321 to accept a high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R
BT.1358.
Follow the specifications in Table 26 when programming the
control signals in async timing mode. For standards that do not
require a trisync level, P_BLANK must be tied low at all times.
Table 26. Async Timing Mode Truth Table
P_HSYNC
P_VSYNC
P_BLANK1
Reference
Reference in Figure 58 and Figure 59
1
→ 0
0
0 or 1
50% point of falling edge of trilevel horizontal sync signal
a
0
→ 1
0 or 1
25% point of rising edge of trilevel horizontal sync signal
b
0
→ 1
0 or 1
0
50% point of falling edge of trilevel horizontal sync signal
c
1
0 or 1
0
→ 1
50% start of active video
d
1
0 or 1
1
→ 0
50% end of active video
e
1 When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 0x10, Bit 6.
CLK
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
81
66
243
1920
HORIZONTAL SYNC
e
d
c
b
a
SET ADDRESS 0x14,
BIT 3 = 1
05067-034
P_HSYNC
P_VSYNC
P_BLANK
Figure 58. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
ACTIVE VIDEO
0
1
HORIZONTAL SYNC
e
d
c
b
a
CLK
SET ADDRESS 0x14
BIT 3 = 1
ANALOG OUTPUT
05067-035
P_VSYNC
P_BLANK
P_HSYNC
Figure 59. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
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