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參數(shù)資料
| 型號： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 44/50頁 |
| 文件大?。?/td> | 408K |
| 代理商： | ADC1443D200HD |
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ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
44 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Table 57.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
SWING_SPARE[2:0]
4 to 0
SWING[4:0]
IP_OUTBUF03_SWING register (address 086Ch) bit description
Access
R/W
R/W
Value
000
001**
Description
Table 58.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
SWING_SPARE[2:0]
4 to 0
SWING[4:0]
IP_OUTBUF04_SWING register (address 086Dh) bit description
Access
R/W
R/W
Value
000
001**
Description
Table 59.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
LANE_LATENCY[2:0]
4 to 3
LANE_MODE[1:0]
2
LANE_POL
1
LANE_CLK_POS_EDGE
0
LANE_PD
IP_LANE0_0_CTRL register (address 0871h) bit description
Access
R/W
R/W
R/W
R/W
R/W
Value
000
00
0
0
*
Description
Table 60.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
LANE_LATENCY[2:0]
4 to 3
LANE_MODE[1:0]
2
LANE_POL
1
LANE_CLK_POS_EDGE
0
LANE_PD
IP_LANE1_0_CTRL register (address 0872h) bit description
Access
R/W
R/W
R/W
R/W
R/W
Value
000
00
0
0
*
Description
Table 61.
Default settings are shown highlighted.
Bit
Symbol
7 to 6
-
5 to 4
ADC_MODE[1:0]
3 to 1
-
0
ADC_PD
IP_ADCA_0_CTRL register (address 0890h) bit description
Access
-
R/W
-
R/W
Value
00
00
000
0
Description
not used
not used
Table 62.
Default settings are shown highlighted.
Bit
Symbol
7 to 6
-
5 to 4
ADC_MODE[1:0]
3 to 1
-
0
ADC_PD
IP_ADCB_0_CTRL register (address 0891h) bit description
Access
-
R/W
-
R/W
Value
00
00
000
0
Description
not used
not used
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