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| 型號(hào)： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁(yè)數(shù)： | 43/50頁(yè) |
| 文件大?。?/td> | 408K |
| 代理商： | ADC1443D200HD |
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ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
43 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Table 51.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
CTRL_SPARE[2:0]
4 to 2
PREEMPH_CTRL[2:0]
1
PREEMPH_PD
0
FULL_PD
IP_OUTBUF01_CTRL register (address 0860h) bit description
Access
R/W
R/W
R/W
R/W
Value
000
000
0
0
Description
Table 52.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
CTRL_SPARE[2:0]
4 to 2
PREEMPH_CTRL[2:0]
1
PREEMPH_PD
0
FULL_PD
IP_OUTBUF02_CTRL register (address 0861h) bit description
Access
R/W
R/W
R/W
R/W
Value
000
000
0
0
Description
Table 53.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
CTRL_SPARE[2:0]
4 to 2
PREEMPH_CTRL[2:0]
1
PREEMPH_PD
0
FULL_PD
IP_OUTBUF03_CTRL register (address 0862h) bit description
Access
R/W
R/W
R/W
R/W
Value
000
000
0
0
Description
Table 54.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
CTRL_SPARE[2:0]
4 to 2
PREEMPH_CTRL[2:0]
1
PREEMPH_PD
0
FULL_PD
IP_OUTBUF04_CTRL register (address 0863h) bit description
Access
R/W
R/W
R/W
R/W
Value
000
000
0
0
Description
Table 55.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
SWING_SPARE[2:0]
4 to 0
SWING[4:0]
IP_OUTBUF01_SWING register (address 086Ah) bit description
Access
R/W
R/W
Value
000
001**
Description
Table 56.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
SWING_SPARE[2:0]
4 to 0
SWING[4:0]
IP_OUTBUF02_SWING register (address 086Bh) bit description
Access
R/W
R/W
Value
000
001**
Description
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