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| 型號(hào)： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁(yè)數(shù)： | 33/50頁(yè) |
| 文件大?。?/td> | 408K |
| 代理商： | ADC1443D200HD |
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11.5.2
Register allocation map
A
A
O
R
3
N
A
D
Table 19
shows an overview of all registers.
Table 19.
Addr.
(hex)
Register allocation map
Register name
R/W
Bit definition
Bit 4
Default
Bin
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Hex
ADC control registers
0000h CHIP_RESET
RW
SW_RST[7:0]
0000
0000
0100
0011
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0100
0000
0000
00h
0001h CHIP_ID
R
CHIP_ID[7:0]
[1]
43h
0005h CHIP_RESET
R/W
SW_RST
-
-
-
-
-
-
-
00h
0006h
[2]
OP_MODE
R/W
-
-
-
-
-
-
OP_MODE[1:0]
[3]
00h
0007h CLK_CFG
R/W
-
-
-
SE_SEL
DIFF_SE
CLK_DIV[2:0]
00h
0008h INTERNAL_REF
R/W
-
-
-
-
-
INTREF[2:0]
00h
0009h CHANNEL_SEL
R/W
-
-
-
-
-
-
ADC_B
ADC_A
0Fh
0011h
OUTPUT_CFG
R/W
-
-
-
-
-
DATA_SWAP
DATA_FORMAT[1:0]
00h
0013h DIG_OFFSET
R/W
DIG_OFFSET[5:0]
-
-
00h
0014h TEST_CFG_1
R/W
-
-
-
-
-
TEST_PAT_SEL[2:0]
00h
0015h TEST_CFG_2
R/W
TEST_PAT_USER[13:6]
00h
0016h TEST_CFG_3
R/W
TEST_PAT_USER[5:0]
-
-
00h
0017h OTR_CFG
R/W
-
-
-
-
FAST_
OTR
-
FAST_OTR_DET[2:0]
14h
00FFh TRANS_CFG
R/W
TRANS_
DIS
TRANSFER
-
-
-
-
-
00h
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|---|---|
| ADC1443D200HD-C1 | 制造商:Integrated Device Technology Inc 功能描述:HLQFN56R - Bulk |
| ADC1443D200W1-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D200W4-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D200WO-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D250HD-C1 | 功能描述:IC ADC 14BIT 2CH 250MSPS 56HLQFN 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:348 |
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