- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382831 > ADC1443D200HD (NXP Semiconductors N.V.) Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs PDF資料下載
參數(shù)資料
| 型號(hào)： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁(yè)數(shù)： | 36/50頁(yè) |
| 文件大?。?/td> | 408K |
| 代理商： | ADC1443D200HD |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)當(dāng)前第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
36 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11.5.3
Detailed register description
The tables in this section contain detailed descriptions of the registers.
11.5.3.1
ADC control registers
[1]
Local register.
Table 20.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
SW_RST
CHIP_RESET register (address 0000h) bit description
Access
R/W
Value
-
Description
resets global and local registers for any value “1”
written at any bit (autoclear).
Table 21.
Default settings are shown highlighted.
Bit
Symbol
7
SW_RST
CHIP_RESET register (address 0005h) bit description
Access
R/W
Value
Description
resets global and local registers
no reset
performs a reset to the default values (autoclear)
not used
0
1
-
6 to 0
-
-
Table 22.
Default settings are shown highlighted.
Bit
Symbol
7 to 2
-
1 to 0
OP_MODE[1:0]
[1]
OP_MODE register (address 0006h) bit description
Access
-
R/W
Value
-
Description
not used
operating mode for the selected channel
normal (power-up)
power-down
sleep
not used
00
01
10
11
Table 23.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
-
4
SE_SEL
CLK_CFG register (address 0007h) bit description
Access
-
R/W
Value
-
Description
not used
single-ended clock input pin selection
CLKP
CLKM
differential/single-ended clock input selection
fully differential
single-ended
0
1
3
DIFF_SE
R/W
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC1610S065HN | Single 16-bit ADC 65 Msps CMOS or LVDS DDR digital outputs |
| ADC1610S065HN | Single 16-bit ADC 65 Msps CMOS or LVDS DDR digital outputs |
| ADC1610S080HN | Single 16-bit ADC 80 Msps CMOS or LVDS DDR digital outputs |
| ADC1610S105HN | Single 16-bit ADC 105 Msps CMOS or LVDS DDR digital outputs |
| ADC1610S125HN | Single 16-bit ADC 125 Msps CMOS or LVDS DDR digital outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1443D200HD-C1 | 制造商:Integrated Device Technology Inc 功能描述:HLQFN56R - Bulk |
| ADC1443D200W1-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D200W4-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D200WO-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D250HD-C1 | 功能描述:IC ADC 14BIT 2CH 250MSPS 56HLQFN 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:348 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。