參數(shù)資料
型號: ADC1443D200HD
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁數(shù): 14/50頁
文件大小: 408K
代理商: ADC1443D200HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
14 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
10.2 Timing
10.2.1
Clock timing
Table 7.
Symbol
t
lat(data)
[1]
Typical values measured at V
DDA
= V
DDO
= 1.8 V; T
amb
= 25
C; minimum and maximum values are across
the full temperature range T
amb
=
40
C to 85
C at V
DDA
= V
DDO
= 1.8 V; V
I(dif)
= 2 V;
V
INP
V
INM
=
1 dBFS; unless otherwise specified.
10.2.2
SYSREF timing
Table 8.
Symbol
t
su
t
h
Clock and digital output timing characteristics
[1]
Parameter
Conditions
data latency time
Min
-
Typ
<tbd>
Max
-
Unit
clock
cycles
ns
ns
ns
t
wake
wake-up time
from Power-down mode
from Sleep mode
from high impedance
-
-
-
<tbd>
<tbd>
<tbd>
-
-
-
Clock timing
f
s
sampling rate
ADC1443D125
ADC1443D160
ADC1443D200
<tbd>
<tbd>
<tbd>
<tbd>
30
-
-
-
-
-
-
<tbd>
125
160
200
1.2
70
-
MHz
MHz
MHz
GHz
%
ns
f
clk
clk
t
d(s)
clock frequency
clock duty cycle
sampling delay time
Fig 3.
Clock and digital output timing
aaa-000418
t
d(s)
t
s
N
N + 1
N + 2
CLKP
CLKM
SYSREF timing
Parameter
set-up time
hold time
Conditions
Min
<tbd>
<tbd>
Typ
-
-
Max
-
-
Unit
ns
ns
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