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參數(shù)資料
| 型號： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 40/50頁 |
| 文件大?。?/td> | 408K |
| 代理商： | ADC1443D200HD |
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ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
40 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11.5.3.2
JESD204A/JESD204B control registers
Table 33.
Default settings are shown highlighted.
Bit
Symbol
7 to 4
-
3 to 0
IP_DIG_ID[3:0]
IP_DIGITAL_ID register (address 0800h) bit description
Access
-
R/W
Value
1010
****
Description
not used
Table 34.
Default settings are shown highlighted.
Bit
Symbol
7
RXSYNC_ERR_FLG
6 to 4
RES_BONDING[2:0]
3 to 2
-
1
POR_TST
0
PLL_INLOCK
IP_STATUS register (address 0801h) bit description
Access
R/W
R/W
-
R/W
R/W
Value
0
000
0
0
0
Description
not used
power-on reset
Table 35.
Default settings are shown highlighted.
Bit
Symbol
7
SW_RST
IP_RESET register (address 0802h) bit description
Access
R/W
Value
0
Description
initiates a software reset of the
JEDEC204A/JESD204B unit
not used
initiates a software reset of the internal state
machine of JEDEC204A/JESD204B unit
not used
6 to 4
3
-
FSM_SW_RST
-
R/W
000
0
2 to 0
-
-
000
Table 36.
Default settings are shown highlighted.
Bit
Symbol
7 to 4
-
3 to 0
CFG_SETUP[3:0]
IP_CFG_SETUP register (address 0803h) bit description
Access
-
R/W
Value
0000
****
Description
not used
Table 37.
Default settings are shown highlighted.
Bit
Symbol
7
ADC_DIRECT_SCSB
6
TRISTATE_CFG_PATH
5
SYNC_POL
4
SYNC_SE
3
EN_RSSYNC_ERR
2
REV_SCR_IN
1
REV_ENC_IN
0
REV_SER_IN
IP_CTRL1 register (address 0805h) bit description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0 (1 > 0)
0
0
1
0
0
1
Description
synchronization polarity
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