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參數(shù)資料
| 型號(hào)： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁(yè)數(shù)： | 42/50頁(yè) |
| 文件大?。?/td> | 408K |
| 代理商： | ADC1443D200HD |
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ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
42 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
2
1
0
PLL_INLOCK_BYPASS
PLL_TST_EN
PLL_PD
R/W
R/W
R/W
0
*
*
Table 44.
Default settings are shown highlighted.
Bit
Symbol
IP_PLL_CTRL1 register (address 080Ch) bit description
…continued
Access
Value
Description
Table 45.
Default settings are shown highlighted.
Bit
Symbol
7 to 3
PLL_CAL_CNTR[7:3]
2 to 0
PLL_P[2:0]
IP_PLL_CTRL2 register (address 080Dh) bit description
Access
R/W
R/W
Value
10000
000
Description
Table 46.
Default settings are shown highlighted.
Bit
Symbol
7 to 2
-
1 to 0
PATTERN_OUT[9:8]
IP_DEBUG_OUT1 register (address 0816h) bit description
Access
-
R/W
Value
000000
10
Description
not used
Table 47.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PATTERN_OUT[7:0]
IP_DEBUG_OUT2 register (address 0817h) bit description
Access
R/W
Value
1010 1010
Description
Table 48.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PATTERN_IN[15:8]
IP_DEBUG_IN1 register (address 0818h) bit description
Access
R/W
Value
1010 1010
Description
Table 49.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PATTERN_IN[7:0]
IP_DEBUG_IN2 register (address 0819h) bit description
Access
R/W
Value
0000 0010
Description
Table 50.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
SPARE_DEBUG[7:5]
4
SYNC_TAP_EN
3 to 0
SYNC_TAP_SEL[3:0]
IP_SPARE_DEBUG register (address 081Ah) bit description
Access
R/W
R/W
R/W
Value
<tbd>
<tbd>
<tbd>
Description
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