參數(shù)資料
型號: ADC1443D200HD
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁數(shù): 25/50頁
文件大?。?/td> 408K
代理商: ADC1443D200HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
25 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11.2.2
Equivalent input circuit
Figure 32
shows the equivalent circuit of the input clock buffer. The input signal must be
AC-coupled and the common-mode voltage of the differential input stage is set via internal
5 k
resistors.
11.2.3
Clock input divider
The ADC1443D contains an input clock divider that divides the incoming clock (clock
frequency f
clk
) by a factor of 1 to 8. it outputs the sampling clock (sampling frequency f
s
)
(see bits CLK_DIV[1:0] in
Table 23
). This feature delivers a higher clock frequency with
better jitter performance, leading to a better SNR result once acquisition has been
performed.
11.2.4
Multi-device synchronization (pins SYSREF, SYSREFN and SYSREFP)
The multi-device synchronization can be controlled with a single-ended or a differential
SYSREF signal.
A high level on SYSREF resets the clock divider phase registers. In a multi-device
application and when the clock divider factor is higher than 1, the ADC1443D
synchronization aligns all sampling clock edges (see
Table 8
and
Figure 4
).
11.3 Digital outputs
11.3.1
Digital output buffers
The JESD204A/JESD204B standard specifies that both the receiver and the transmitter
must be provided by the same supply if they are connected in DC-coupling.
Fig 32. Equivalent input circuit
CLKP
CLKM
001aan476
PACKAGE
ESD
PARASITICS
5 k
Ω
V
cm(clk)
5 k
Ω
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