參數(shù)資料
型號: ADC1443D200HD
廠商: NXP Semiconductors N.V.
元件分類: 外設及接口
英文描述: Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁數(shù): 20/50頁
文件大小: 408K
代理商: ADC1443D200HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
20 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11. Application information
11.1 Analog inputs
11.1.1
Input stage
The analog input of the ADC1443D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with respect to the
common-mode input voltage (V
I(cm)
) on pins INP and INM.
The equivalent circuit of the sample and hold input stage, including ElectroStatic
Discharge (ESD) protection and circuit and package parasitics, is shown in
Figure 24
.
The sample phase occurs when the internal sampling clock (derived from the clock signal
on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When
the sampling clock signal becomes LOW, the device enters the hold phase and the
voltage information is transmitted to the ADC core.
11.1.2
Common-mode input voltage (V
I(cm)
)
Set the common-mode input voltage (V
I(cm)
) on pins INP and INM externally to 0.9 V for
optimal performance.
11.1.3
Pin VCM
When the input stage is AC-coupled, pin VCM can be used to set the common-mode
reference for the analog inputs, for instance, via a transformer middle point. Connect a
0.1
F filter capacitor between pin VCM and ground to ensure a low-noise common-mode
output voltage.
Fig 24. Input sampling circuit
001aan472
INP
PACKAGE
ESD
PARASITICS
SWITCH
Ron = 15
Ω
4 pF
4 pF
SAMPLING
CAPACITOR
SAMPLING
CAPACITOR
SWITCH
Ron = 15
Ω
INM
INTERNAL
CLOCK
INTERNAL
CLOCK
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