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| 型號： | ADC1443D200HD |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual channel 14-bit ADC; 200 Msps; JESD204B-compliant CGVxpress? serial outputs |
| 封裝： | ADC1443D200HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 15/50頁 |
| 文件大小： | 408K |
| 代理商： | ADC1443D200HD |
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ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
15 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
10.2.3
SPI timing
Table 9.
Symbol
t
w(SCLK)
t
w(SCLKH)
t
w(SCLKL)
t
su
[1]
Typical values measured at V
DDA
= V
DDO
= 1.8 V; T
amb
= 25
C; minimum and maximum values are across
the full temperature range T
amb
=
40
C to +85
C at V
DDA
= V
DDO
= 1.8 V
Fig 4.
SYSREF timing
aaa-000419
CLKP-CLKM
SYSREF
50 %
70 %
70 %
t
su
t
h
SPI timing characteristics
[1]
Parameter
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
Conditions
Min
40
16
16
5
5
2
2
-
Typ
-
-
-
-
-
-
-
-
Max
-
-
-
-
-
-
-
25
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
SDIO to SCLK HIGH
SCS_N to SCLK HIGH
SDIO to SCLK HIGH
SCS_N to SCLK HIGH
t
h
hold time
f
clk
clock frequency
Fig 5.
SPI timing
t
su
t
h
SDIO
SCLK
R/W
W1
W0
A12
A11
D2
D1
D0
t
su
t
h
t
w(SCLK)
001aan454
SCS_N
t
w(SCLKL)
t
w(SCLKH)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1443D200HD-C1 | 制造商:Integrated Device Technology Inc 功能描述:HLQFN56R - Bulk |
| ADC1443D200W1-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D200W4-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D200WO-DB | 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits) |
| ADC1443D250HD-C1 | 功能描述:IC ADC 14BIT 2CH 250MSPS 56HLQFN 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:348 |
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