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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大小： | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 22
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
7 R
ESET
C
ONFIGURATION
7.1
After a hardware reset, all writable registers are reset to
0x00, with the following exceptions:
1. DLL which is reset to 0x01.
2. MCR[7] is reset to the complement of the CLKSEL
input pin value (see section 11.1 ).
3. CPR is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indetermnate
RFL[6:0]: 0000000
2
TFL[6:0]: 0000000
2
LSR[7:0]: 0x60 signifying that both the transmtter and the
transmtter FIFO are empty
MSR[3:0]: 0000
2
MSR[7:4]: Dependent on modeminput lines DCD, RI,
DSR and CTS respectively
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx00000
2
RFC[7:0]: 00000000
2
GDS[7:0]: 00000001
2
DMS[7:0]: 00000010
2
CKA[7:0]: 00000000
2
The reset state of output signals are tabulated below:
Signal
SOUTn
RTSn#
DTRn#
INTn /
IRQ#
otherwise high-impedance
RXRDY#
TXRDY#
Active low (THR is able to receive data).
Hardware Reset
Reset state
Inactive High
Inactive High
Inactive High
Inactive low when INTSEL#pin is held high
Inactive High
Table 8: Output Signal Reset State
7.2
An additional feature available in the OX16C954 device is
independent software resetting of any of the four serial
channels. The software reset is available using the given
channels CSR register.
The Software reset command has the same effect as a
hardware reset except it only resets the channel whose
CSR register is written, the state of all other channels
remains unchanged. Also it does not reset the clock source
selections (i.e. CKS register and CKA register). To reset a
channel, write 0x00 to the Channel Software Reset register
‘CSR’.
Software Reset
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