
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 29: Endian Mode
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
29-6
An interesting example is the small C program below that determines whether the
program runs on a big-endian or little-endian mode machine.
int w = 0x04050607;
char *a = (char *) &w;
if (*a == 0x04) printf("big-endian"); else printf("little-endian");
3.2 Law 2: The “DMA Convention Rule”
The DMA convention rule says that “when a stream of items enters the system, items
should be placed in memory such that an item that arrived later has a higher address
value.” On output, a similar convention holds—items sent rst are those with the
lowest addresses.
A variant of this rule relates to the storage of images. Pixels from left to right have
increasing addresses. Lines from top to bottom have increasing addresses.
This is a convention that keeps programmers sane. It may also be seen as arbitrary,
but obviously the best choice between two alternatives.
A more precise version of this rule is:
If item ’0’ of a DMA item stream is placed at address “A,” item “i” of a DMA stream
should be placed at byte address “A+i*s,” where “s” is the item size in bytes.
Table 3: Register Result of a (Signed) Load Instruction
Memory Content
Endian
Mode
Data Size
Register Value Result of
Loadsize(address a)
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
little
8 bits
0xFFFFFFAA
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
little
16 bits
0xFFFFBBAA
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
little
32 bits
0xDDCCBBAA
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
big
8 bits
0xFFFFFFAA
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
big
16 bits
0xFFFFAABB
m[a] = 0xAA; m[a+1] = 0xBB; m[a+2] = 0xCC; m[a+3] = 0xDD
big
32 bits
0xAABBCCDD
Figure 4:
Memory Content Created by the C Program
int w = 0x04050607;
char *a = (char *)&w;
04
05
06
07
Big-Endian Mode Memory Content
Little-Endian Mode Memory Content
a+0
04
05
06
07
a+3
a+1
a+2
a+3
a+2
a+1
a+0
0
31
04
05
06
07
CPU Register Content