
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
23-6
The register map of the LAN100 includes MII Interface registers and registers for
controlling DMA transfers, ow control and ltering. It also includes interrupt control
and module ID registers.
Table 1 provides a summary of all LAN100 registers.
Table 1: LAN100 MMIO Register Map
Offset
Name
R/W
Function
MII Interface
0x07 2000
MAC1
R/W
MAC Conguration register 1
0x07 2004
MAC2
R/W
MAC Conguration register 2
0x07 2008
IPGT
R/W
Back-to-back Inter-packet Gap register
0x07 200C
IPGR
R/W
Non B2B Inter-packet Gap register
0x07 2010
CLRT
R/W
Collision Window / Retry register
0x07 2014
MAXF
R/W
Maximum frame register
0x07 2018
SUPP
R/W
PHY Support register
0x07 201C
TEST
R/W
Test register
0x07 2020
MCFG
R/W
MII Management Conguration register
0x07 2024
MCMD
R/W
MII Management Command register
0x07 2028
MADR
R/W
MII Management Address register
0x07 202C
MWTD
WO
MII Management Write Data register
0x07 2030
MRDD
RO
MII Management Read Data register
0x07 2034
MIND
RO
MII Management Indicators register
0x07 2038
Reserved
0x07 203C
Reserved
0x07 2040
SA0
R/W
Station Address 0 register
0x07 2044
SA1
R/W
Station Address 1 register
0x07 2048
SA2
R/W
Station Address 2 register
0x07 204C
to
0x07 20FC
Reserved
Control Registers
0x07 2100
Command
R/W
Command register
0x07 2104
Status
RO
Status register
0x07 2108
RxDescriptor
R/W
Receive Descriptor Base Address register
0x07 210C
RxStatus
R/W
Receive Status Base Address register
0x07 2110
RxDescriptorNumber
R/W
Number of Receive Descriptors register
0x07 2114
RxProduceIndex
RO
Receive Produce Index register
0x07 2118
RxConsumeIndex
R/W
Receive Consume Index register
0x07 211C
TxDescriptor
R/W
Non Real-Time Transmit Descriptor Base
Address register
0x07 2120
TxStatus
R/W
Non Real-Time Transmit Status Base Address
register