
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
3-9
4.1 System Endian Mode MMIO registers
5.
System Semaphores
PNX15xx Series has 16 simple Multi-Processor (MP) semaphore-assist devices.
They are built out of 32-bit registers, accessible through MMIO by either the local
TM3260 CPU or by any other CPU located on the PCI bus through the aperture made
available on the PCI module.
The semaphores operation is as follows: each master in the system constructs a
personal nonzero 12-bit ID
(Section 5.2). To obtain a semaphore, a master is required
to do the following actions:
write the unique ID to one of the 16 semaphores using a 32-bit store. This uses a
32-bit write with the ID in the 12 LSBs
read back the ID. This uses a 32-bit load that returns 0x00000nnn. Then
if (0x00000nnn == ID) {
“perform the short critical section action for which the semaphore was
requested”;
“then write 0x00000000 back to the selected semaphore to release it for the
other tasks”
} else {“try again later, or loop back to write”}
5.1 Semaphore Specication
Each of the 16 semaphores behavior is dened by the following pseudo-code:
if (cur_content == 0) {
new_content = write_value;
} else {if (write_value == 0) new_content = 0;}
/* ELSE NO ACTION! */
Layout and offset address of the 16 semaphores is available in
Section 5.5.5.2 Construction of a 12-bit ID
A system based on PNX15xx Series can construct a personal, non-zero 12-bit ID in a
variety of ways:
Table 3: SYSTEM REGISTERS
Bit
Symbol
Acces
s
Value
Description
System Endian Mode Registers
Offset 0x06 3014
SYS_ENDIANMODE
31:1
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
0
BIG_ENDIAN
R/W
0
System endian mode.
‘0’: little endian.
‘1’: big endian.