
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
18-12
registers are updated with user data bits information from the
previous block. The
meaning of the user data is application dependent. The SPDI_CTL.UCBITS_SEL
register determines which set (subframe 1 or 2) of 192 user data bits will be captured.
3.2.8
SPDI_BASEx and SPDI_SIZE Registers and Memory Buffers
SPDI_BASE1 and SPDI_BASE2 are used to select the main memory buffer starting
addresses used for DMA of audio data samples. At the start of SPDIF Input capture,
the hardware will begin lling the memory buffer beginning at the address specied in
the SPDI_BASE1 register. Once this buffer is lled, the hardware will switch buffers
and begin lling the memory buffer starting at the address specied in the
SPDI_BASE2 register. The size of these DMA buffers is specied in the SPDI_SIZE
register. Note that the hardware limits the buffer size and starting address to be
aligned to 64 byte addresses. Assignment to SPDI_BASE1, SPDI_BASE2 and
SPDI_SIZE have no effect on the state of the SPDI_STATUS ags. Any change to the
SPDI_BASE1 or SPDI_BASE2 registers should only be done while a memory buffer
is not being used by the hardware DMA.
3.2.9
SPDI_SMPMASK and Sample Size Masking
The SPDI_SMPMASK register allows per bit masking the
least signicant 8 bits of the
incoming samples (corresponding to subframe bits [11:4]). The SMASK setting
only
applies to 32-bit capture mode (i.e. SAMP_MODE = 01). The 8 bits of SMASK will
determine which subframe bits [11:4] will be captured and stored in memory. To reject
a particular bit (
within subframe bits [11:4]) in an audio sample, set the corresponding
SMASK[7:0] bit to logic ‘1’. The default value of SMASK is 0x00.
Note the sense of the mask operation! Setting SMASK[7:0] bits to logic ‘1’ will zero
the corresponding subframe bit [11:4]. Others will pass unchanged!
Ex 1. The capture mode is congured for 32-bit stereo capture (SAMP_MODE = 01
and CHAN_MODE = 00). It is desired to store only 20 bit sample pairs. The left/right
channels incoming subframe bits [27:4] consist of a 24 bit samples of the form L =
0xABCDEF and R = 0x123456 respectively. To retain the most signicant 20 bits (i.e.
keep ‘ABCDE’ in the left sample and ‘12345’ in the right sample) and write them to
memory, set the SMASK[7:0] bits to ‘0x0F’. During capture and once the samples are
masked, the least signicant ends are zero extended to 32 bits. The result is a 32 bit
sample pair of the form L = ‘0xABCDE000’ and R = ‘0x12345000’. The samples are
nally stored in memory subject to endian control.
The masking operation applies to all memory bound samples.
3.2.10
SPDI_BPTR and the Start of an IEC60958 Block
During SPDIF Input capture, memory buffers are continuously lled with input data.
As input blocks are lling the memory buffers, the address of the rst instance of a
frame 0 in a particular memory buffer changes continuously. To aid software with the
task of nding the start of a block in memory, the SPDI_BPTR contains the address of
the rst occurrence of a frame 0 (indicating the starting boundary of a complete 192
frame block) within the last lled memory buffer - either BUF1 or BUF2. This function
is useful during capture of non-PCM coded data as found in IEC61937 data streams.
The software driver can use SPDI_BPTR to nd the beginning of an IEC60958 block
and then quickly determine the location of any sync condition thereafter embedded in
the non-PCM data structure.