
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
5-9
Run the VCO as high as possible, therefore for low output frequencies chose high
P values
Ensure
and track N with the following current adjustment values:
PLL Settings
An easy way to determine the N over M ratio is to meet the PLL limitations seen
above and solve the following equation:
(6)
PLL Setting Examples
Table 1 presents some other typical examples to set the PLL N, M and P parameters.
PLL2 (for the DDR) has the P parameter wired to ‘1’.
30
N
180
≤≤
Table 2: Current Adjustment Values Based on N
30-37 38-46 47-54 55-63 64-72 73-82 83-89 90-97 98-107 108-116 117-125 126-133 134-142 143-151 152-160 161-180
0xF
0xE
0xD
0xC
0xB
0xA
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
N
M
-----
F
vco
F
in
-----------
=
Table 3: PLL Settings
Fout
Fvco
Fin
M
N
P
ADJ Destination Examples
27 MHz
216 MHz
DDS1
27 MHz
4
0x20
3
0xF
QVCP from DDS1
50% duty cycle recommended
54 MHz
432 MHz
DDS1
27 MHz
3
0x30
3
0xD QVCP from DDS1
50% duty cycle recommended
65 MHz
520 MHz
DDS1
27.012987 MHz
4
0x4D
3
0xA QVCP from DDS1
50% duty cycle recommended
81 MHz
324 MHz
DDS1
27 MHz
3
0x24
2
0xF
QVCP from DDS1
50% duty cycle recommended
133.07 MHz 266.14 MHz 27 MHz CRYSTAL
7
0x45
n/a
0xB DDR266, i.e. <= 133.333333 MHz MM_CK
166.5 MHz
333 MHz
27 MHz CRYSTAL
3
0x25
n/a
0xF
DDR333, i.e. <= 166.666666 MHz MM_CK
181.29 MHz 362.57 MHz 27 MHz CRYSTAL
7
0x5E
n/a
0x8
DDR366, i.e. <= 181.818181 MHz MM_CK
199.8 MHz
399.6 MHz
27 MHz CRYSTAL
5
0x4A
n/a
0xA DDR400, i.e. <= 200.000000 MHz MM_CK
240.3 MHz
480.6 MHz
27 MHz CRYSTAL
5
0x59
1
0x9
240 MHz TM3260, i.e. PNX1500
266.63 MHz 533.25 MHz 27 MHz CRYSTAL
4
0x4F
1
0xA 266 MHz TM3260, i.e. PNX1501 or PNX1520
300.38 MHz 600.75 MHz 27 MHz CRYSTAL
4
0x59
1
0x9
300 MHz TM3260, i.e. PNX1502
351 MHz
27 MHz CRYSTAL
3
0x27
0
0xE 350 MHz TM3260, i.e. PNX1503