
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 9: DDR Controller
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
9-24
observe the performance of the DDR SDRAM Controller
observe specics about errors
Turning the DDR controller into halt mode, programming MMIO registers while in halt
mode, and un-halting the DDR controller when the MMIO registers have been
programmed, is the suggested series of actions to change MMIO register values of a
started DDR controller.
5.1 Register Summary
The offsets reported in the following table are absolute offset with respect to the
MMIO_BASE value.
Table 8: Register Summary
Offset
Symbol
Description
0x06 5000
IP_2031_CTL
DDR GENERAL CONTROL
0x06 5004
DDR_DEF_BANK_SWITCH
DDR BANK SWITCH ADDRESSING
0x06 5008
AUTO_HALT_LIMIT
DDR AUTO HALT LIMIT
0x06 5010
RANK0_ADDR_LO
DDR RANK0 ADDRESS LOW LIMIT
0x06 5014
RANK0_ADDR_HI
DDR RANK0 ADDRESS HIGH LIMIT
0x06 5018
RANK1_ADDR_HI
DDR RANK1 ADDRESS HIGH LIMIT
0x06 5080
DDR_MR
DDR MODE REGISTER
0x06 5084
DDR_EMR
DDR EXTEND MODE REGISTER
0x06 5088
DDR_PRECHARGE_BIT
DDR PRECHARGE BIT FIELD
0x06 50C0
RANK0_ROW_WIDTH
DDR RANK0 ROW BIT WIDTH
0x06 50C4
RANK0_COLUMN_WIDTH
DDR RANK0 COLUMN BIT WIDTH
0x06 50D0
RANK1_ROW_WIDTH
DDR RANK1 ROW BIT WIDTH
0x06 50D4
RANK1_COLUMN_WIDTH
DDR RANK1 COLUMN BIT WIDTH
0x06 5100
DDR_TRCD
DDR ACTIVE to READ or WRITE DELAY
0x06 5104
DDR_TRC
DDR ACTIVE to ACTIVE/AUTO REFRESH DELAY
0x06 5108
DDR_TWTR
DDR INTERNAL WRITE to READ COMMAND DELAY
0x06 510C
DDR_TWR
DDR WRITE RECOVERY TIME
0x06 5110
DDR_TRP
DDR PRECHARGE COMMAND PERIOD
0x06 5114
DDR_TRAS
DDR ACTIVE to PRECHARGE COMMAND PERIOD
0x06 511C
DDR_TRRD
DDR ACTIVE BANK A to ACTIVE BANK B COMMAND
0x06 5120
DDR_TRFC
DDR AUTO REFRESH COMMAND PERIOD
0x06 5124
DDR_TMRD
DDR LOAD MODE REGISTER COMMAND CYCLE
0x06 5128
DDR_TCAS
DDR CAS READ LATENCY
0x06 512C
DDR_RF_PERIOD
DDR REFRESH PERIOD
0x06 5180
ARB_CTL
DDR ARBITER CONTROL
0x06 5184
ARB_HRT_WINDOW
DDR ARBITER HARD REAL TIME WINDOW
0x06 5188
ARB_CPU_WINDOW
DDR ARBITER CPU WINDOW