
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
18-7
or 0.26UI pk-pk (1 UI = 1/128
Fs). For a particular Fs, the max jitter is shown in
The SPDIF Input receiver will reproduce the input data and clock without error if the
maximum input jitter remains within the specied max jitter tolerance above. The
receiver design meets and exceeds the IEC60958-3 consumer jitter requirements
specication (i.e
0.25 UI pk-pk between 200 Hz and 400 kHz jitter freq.).
3.1.4
SPDIF Input and the Oversampling Clock
The oversampling clock supplied to the input receiver is derived from a divider in the
central clock control block. The divider value to select is determined by
Table 1. Once
the oversampling clock has been selected by programming a divider value, the
condition of the LOCK bit status indicator in SPDI_STATUS provides feedback on
whether the selected oversampling clock has allowed the interface to achieve lock
onto the incoming SPDIF input stream. The settings provided by the divider for the
oversampling clock are sufcient for capture of 32 kHz, 44.1 kHz, 48 kHz and 96 kHz
sample rate input streams.
3.2 Register Programming Guidelines
3.2.1
SPDIF Input Register Set
page 18-16. The register set is composed of status and control functions necessary
to congure SPDIF Input data capture and DMA of audio data to main memory. To
ensure compatibility with future devices, any reserved MMIO register bits in
Figure 9ignored when read, and written as zeroes.
Table 2: Input Jitter for Different Sample Rates
Fs (kHz)
1 UI = 1/(128 Fs) (nsec)
Max Jitter = 0.26UI pk-pk (nsec)
32
244.1
31.7
44.1
177.2
23.0
48
162.8
21.2
96
81.4
10.6
Figure 6:
SPDIF Input Oversampling Clock Generation
Divide by n
432MHz (16x27MHz)
PIN
SPDI_IN
Central clocking domain
n = 3, 6
SPDIF Input domain
SPDIF Input
Receiver
SPDIF Input
Decoder
Memory Bound
Audio Data
oversampling
clock