
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
18-21
7
LOCK
R
0
LOCK active
1 = The SPDIF Input receiver achieved lock onto the incoming
stream. Use this LOCK ag, in conjunction with the UNLOCK ag,
to determine the state of the receiver or to make a decision to adjust
the oversampling frequency. The ag can be cleared by a software
write to LOCK_CLR. LOCK means that the internal PLL is locked. A
valid sequence of preambles is not required for LOCK.
6
VERR
R
0
Validity Error
1 = The hardware encounters a subframe that has the validity ag
set to 1, indicating that the payload portion of the subframe is not
reliable. The ag can be cleared by a software write to VERR_CLR.
5
PERR
R
0
Parity Error
1 = The hardware encounters a subframe that has a parity error.
Parity is even for the subframe and applies to subframe bits [31:4]
inclusive. Normally, the external SPDIF Input transmitter will set the
subframe P bit to logic ‘1’ or logic ‘0’ so that bits [31:4] have an even
number of logic “1s” and “0s”. The ag can be cleared by a software
write to PERR_CLR.
4
OVERRUN
R
0
1 = Both external main memory DMA buffers are lled before a new
empty buffer is assigned by the system control CPU. Hardware has
performed a normal buffer switch over and is overwriting fresh,
unconsumed data. This ag can be cleared by software write to
OVR_CLR.
3
HBE (Bandwidth error)
R
0
Bandwidth Error
1 = The internal hardware DMA buffers in SPDI are full and at least
one of them was not emptied before new input data arrived on the
SPDI interface, indicating that DMA service latency is too long. This
ag can be cleared by a software write to HBE_CLR.
2
BUF1_ACTIVE
R
0
This ag is set to logic ‘1’ if the hardware is currently lling memory
DMA buffer 1. Otherwise, it is reset to logic ‘0’. This ag can be
cleared by a software write to BUF1_ACTIVE_CLR.
1
BUF2_FULL
R
0
This ag is set to logic ‘1’ if memory DMA buffer 2 has been lled by
the SPDI hardware. It can be cleared by a software write to
BUF2_FULL_CLR.
0
BUF1_FULL
R
0
This ag is set to logic ‘1’ if memory DMA buffer 1 has been lled by
the SPDI hardware. It can be cleared by a software write to
BUF1_FULL_CLR.
Offset 0x10 AFE4
SPDI_INTEN
31:10
Unused
-
9
UNLOCK_ENBL
R/W
0
1 = UNLOCK bit in SPDI_STATUS is enabled for interrupts.
0 = UNLOCK bit in SPDI_STATUS is disabled for interrupts.
8
UCBITS_ENBL
R/W
0
1 = UCBITS bit in SPDI_STATUS is enabled for interrupts.
0 = UCBITS bit in SPDI_STATUS is disabled for interrupts.
7
LOCK_ENBL
R/W
0
1 = LOCK bit in SPDI_STATUS is enabled for interrupts.
0 = LOCK bit in SPDI_STATUS is disabled for interrupts.
6
VERR_ENBL
R/W
0
1 = VERR bit in SPDI_STATUS is enabled for interrupts.
0 = VERR bit in SPDI_STATUS is disabled for interrupts.
Table 6: SPDIF Input Registers …Continued
Bit
Symbol
Acces
s
Value
Description