
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
3-4
Remark: If the value 0x0000,0000 is stored into TM32_APERT1_HI, this value is
understood as 0x1,0000,0000.
2.3 The DCS View Or The System View
The DCS bus can be seen as the link between the PCI side and the CPU side:
Requests from the PCI bus or the TM3260 targeting the MMIO aperture converge
to the DCS bus through the MMIO apertures and then are dispatched to the
corresponding MMIO registers.
Requests from the TM3260 to the APERT1 aperture are transferred to the DCS
bus and then dispatched to the PCI module if the address of the request matches
one of the three apertures, PCI2, PCI1 or XIO. These apertures are used to map
loads and stores from the CPU to any slave connected to the PCI bus. The
denition of the MMIO registers containing the address ranges for the two
Remark: Requests from the TM3260 to APERT1 may fall in an non accessible
address region in the DCS bus, like between the PCI1 and PCI2 apertures. It is legal
to do so. The request is discarded by the DCS bus controller and a random value is
returned upon reads.
Remark: TM3260 compiler uses speculative loads (i.e. the result of the load may not
be used by the CPU) to improve performance. These speculative loads often contain
addresses coming from the TM3260 internal register file that are not initialized
properly since the return value of the load is not to be used (unless the execution of
Figure 2:
PNX15xx Series System Memory Map
0x0000 0000
inaccessible
MMIO_BASE/base_14
MMIO Aperture
TM32_APERT1_HI
TM32_APERT1_LO
APERT1 Aperture
0x1 0000 0000
inaccessible
2MB
inaccessible
TM32_DRAM_HI
TM32_DRAM_LO
DRAM Aperture
TM32_DRAM_CLIMIT
non-cacheable
0x0000 0000
inaccessible
base_14
MMIO Aperture
PCI_BASE1_LO
base_18
XIO Aperture
0x1 0000 0000
inaccessible
2MB
inaccessible
DCS_DRAM_HI
DCS_DRAM_LO
DRAM Aperture
inaccessible
MMIO Aperture
inaccessible
2MB
inaccessible
DRAM Aperture
BASE_10
BASE_18
BASE_14
PCI1 Aperture
PCI2 Aperture
PCI_BASE1_HI
PCI_BASE2_LO
PCI_BASE2_HI
XIO Aperture
PCI1 Aperture
PCI2 Aperture
0x1 0000 0000
0x0000 0000
TM3260
DCS
PCI