
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 16: Audio Input
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
16-4
Raw sample mode where the serial data for each active serial channel is
sampled at each sampling clock edge along with the AI_WS and transferred to
memory as a byte.
2.2 General Operations
Software initiates capture by providing two equal size empty buffers and putting their
base address and size in the BASE1, BASE2 and SIZE registers. Once two valid
(local memory) buffers are assigned, capture can be enabled by writing a ‘1’ to
CAP_ENABLE. The Audio In unit hardware will proceed to ll buffer 1 with input
samples. Once buffer 1 lls up, BUF1_FULL is asserted, and capture continues
without interruption in buffer 2. If BUF1_INTEN is enabled, a level triggered interrupt
request is generated to the chip level interrupt controller.
Note that the buffers must be 64-byte aligned and must be a multiple of 64 samples in
size (the six LSBits of AI_BASE1, AI_BASE2 and AI_SIZE are always zero).
Software is required to assign a new, empty buffer to BASE1 and perform an ACK1,
before buffer 2 lls up. Capture continues in buffer 2, until it lls up. At that time,
BUF2_FULL is asserted and capture continues in the new buffer 1, etc.
Upon receipt of an ACK, the Audio In hardware removes the related interrupt request
line assertion at the next main clock edge.
In normal operation, the chip level system controller and Audio In hardware
continuously exchange buffers without ever losing a sample. If the system controller
fails to provide a new buffer in time, the OVERRUN error ag is raised. This ag is
not
affected by ACK1 or ACK2; it can only be cleared by an explicit write of logic ‘1’ to
ACK_OVR.
Remark: Reserved bits in MMIO registers should be ignored when read and written