
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
11-57
11:0
LayerNWidth
R/W
0
initial (before scaling) Layer N width, in pixels.
Offset 0x10 E238
Pedestal and O/P format
31:24
Pedestal_up
R/W
0
Pedestal to be added to Upper input
(pedestal_up is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering.
23:16
Pedestal_mid
R/W
0
Pedestal to be added to Middle input
(pedestal_mid is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering
15:8
Pedestal_low
R/W
0
Pedestal to be added to Lower input
(pedestal_low is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering
7:3
Unused
-
2:1
OP_format
R/W
0
Output type selector
0 = data expansion from 8 to 9 bit through multiply by two (zero in
LSB)
1 = data expansion from 8 to 9 bit through multiply by two (MSB
in LSB position)
2,3 = data expansion from 8 to 9 bit through multiply by two
(undither operation)
0
FRMT_4xx
R/W
0
Input format indicator
0 = Input is in 4:4:4 format
1 = Input is in 4:2:2 format
Offset 0x10 E23C
Layer Pixel Processing
31:6
Unused
-
5
Buffer toggle
R/W
0
This bit controls the DMA buffer mode:
1 = Always toggle between buffer A and B (A=odd eld, B=even
eld).
0 = No buffer toggle, always fetch from buffer spec A.
4
Layer_Start_Field
R/W
1
Field in which the layer gets actually enabled once the
LayerN_Enable bit is set. This bit is used to invert the internal odd/
even signal. If the result of the operation Layer_Start_Field xor OE
is true the layer is enabled, otherwise the layer stays disabled until
the OE signal changes.
In non-interlaced modes:
this bit must be set to 1’b1 since the internal odd/even signal is
forced to zero.
In interlaced modes:
LayerNStartY (0x10,E230) >= 0, set this bit to 0
LayerNStartY (0x10,E230) < 0, set this bit to 1
3
Premult
R/W
0
If this bit is set, the incoming pixels are premultiplied with alpha.
That disables the new x alpha multiplication in the mixer stage if
alpha blending is enabled.
Table 20: QVCP 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description