
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
23-73
Disable the Tx DMA managers by setting the Tx(Rt)Enable bits in the Command
register to 0
Set the TxReset bit in the Command register (this bit clears automatically)
Reset the RESET_PEMCS_Tx bit in the MAC1 register to 0.
To reset just the Receive Datapath the device driver software must:
Disable the receive function by resetting the RECEIVE_ENABLE bit in the MAC1
conguration register and resetting of the RxEnable bit of the Command register.
Set the RESET_PEMCS_Rx bit in the MAC1 register to 1
Set the RxReset bit in the Command register (this bit clears automatically)
Reset the RESET_PEMCS_Rx bit in the MAC1 register to 0.
A soft reset of the Transmit Datapaths will abort any transmit-descriptor read,
status-write, and data-read operations.
A soft reset of the Receive Datapath will abort any receive-descriptor read,
status-write and data-write operations.
6.
System Integration
6.1 MII Interface I/O
Table 12 summarizes the pin interface of the LAN100.
Table 12: LAN100 Pin Interface to external PHY
Pin
Directio
n
Description
LAN_CLK
Out
Clock to feed the external PHY, usually 50 MHz
LAN_TX_CLK/LAN_REF_CLK
In
MII Transmit Clock or RMII Reference Clock
LAN_TX_EN
Out
MII or RMII Transmit Enable
LAN_TXD3
LAN_TXD2
LAN_TXD1
LAN_TXD0
Out
MII Transmit Data
MII or RMII Transmit Data
LAN_TX_ER
Out
MII Transmit Error
LAN_CRS/LAN_CRS_DV
In
MII Carrier Sense or RMII Carrier Sense and Receive Data Valid.
This pin is 5 V input tolerant.
LAN_COL
In
Collision Detect. This pin is 5 V input tolerant.
LAN_RX_CLK
In
MII Receive Clock
LAN_RXD3
LAN_RXD2
LAN_RXD1
LAN_RXD0
In
MII Receive Data
MII or RMII Receive Data
LAN_RX_DV
In
MII Receive Data Valid