
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 14: FGPI: Fast General Purpose Interface
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
14-14
3.2 Message Passing Mode
Only active clock edges where fgpi_d_valid is asserted ‘1’ allow data samples to be
captured.
If FGPI_REC_SIZE is not a multiple of 4 bytes, the message will be written to main
memory as a series of 32-bit words. Only the last word is padded with zeroes in the
Message start is signaled on the fgpi_start pin and message stop is signaled on the
fgpi_stop pin. See FGPI_CTL.MSG_START and FGPI_CTL.MSG_STOP for
selecting which edge will be active.
Figure 7 illustrates an example of a two 8-sample message transfer. The message
start event is set to the falling edge of fgpi_start and the message stop event is set to
the rising edge of fgpi_stop.
Message mode requires both fgpi_start and fgpi_stop signals to operate. There is no
external buffer sync available. Buffers are switched when the number of messages
received equals the value programmed into the FGPI_SIZE register.
If the incoming message length is greater than the value programmed into the
FGPI_REC_SIZE register, the message is truncated and the OVERFLOW interrupt is
generated (if enabled).
3.2.1
Minimum Message/Record Size
THE MINIMUM MESSAGE SIZE is 2, that is, FGPI_REC_SIZE must be programmed
greater than 1.
There is a limit to the message size when back-to-back messages are received.
If the sample size is 32-bits AND TSTAMP_SELECT = ‘1’ AND VAR_LENGTH =
‘1’ then the minimum message size is 3 (due to the insertion of 2 32-bit words into
the message packet).
Figure 7:
Back-to-back Message Passing Example
clk_fgpi
fgpi_d_valid
fgpi_start
fgpi_stop
fgpi_data
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D2
D3
D4
D5
D6
D7
D8
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