
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-30
Offset 0x04 0088
PCI_IO
31:24
upper_io3_addr
R/W
0
Bits [31:24] of IO address during PCI IO transactions.
23:16
upper_io2_addr
R/W
0
Bits [23:16] of IO address during PCI IO transactions.
15:3
Reserved
R
0
2
use_io3_addr
R/W
0
Use “upper_io3_addr” as the upper address for PCI IO transactions.
1
use_io2_addr
R/W
0
Use “upper_io3_addr” and “upper_io2_addr” as the upper address
for PCI IO transactions.
0
use_pcibase2_as_io
R/W
0
1: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as IO
transactions. The address will unchanged or modied with an
alternate upper addresses selected above.
0: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as
memory transactions with unchanged address.
Offset 0x04 008C
Slave DTL tuning
31:24
Reserved
R
0
20:16
slv_memrd_fetch
R/W
111
PCI slave DTL read block size for memory read command. Default
value is 8 32-bit words. Maximum is 64 32-bit words.
11:8
slv_threshold
R/W
10
Threshold (amount of data not consumed from previous read
request) for when PCI slave DTL requests more read data when
responding to memory read command. This must be set to a value
less than the smallest of slv_memrd_fetch, Cache Line Size or
read_block_siz. Default is 3 32-bit words. Maximum value is 32 32-
bit words.
7:3
Reserved
R
0
2:0
slv_mrmul_fetch
R/W
001
Encoded PCI slave DTL read block size for memory read multiple
command
siz : read_block_siz
000:
8 bytes
001:
16 bytes
010:
32 bytes
011:
64 bytes
100: 128 bytes
101: 256 bytes
110: 512 bytes
111: 1024 bytes
Offset 0x04 0090
DMA DTL tuning
31:16
Reserved
R
0
15:8
dma_threshold
R/W
0x1B
Threshold for when DMA DTL requests more read data when initial
fetch is less than total dma length.
7:3
Reserved
R
0
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description