
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
3-14
6.2 Timers
The TM3260 CPU contains four programmable timer/counters, all with the same
function. The rst three (TIMER1, TIMER2, TIMER3) are intended for general use.
The fourth timer/counter (SYSTIMER) is reserved for use by the system software and
should not be used by applications.
Each timer/counter can be set to count one of the event types specied in
Table 6.Note that source 3 to 6 are special TM3260 events used for program debug support
as well as cache performance monitoring. Full description can be found in [1]. For all
the other source signals, like the VDO_CLK1 pin, positive-going edges on the signal
are counted. Each timer increments its value until the programmed count is reached.
On the clock cycle when the timer reaches its programmed count value, an interrupt
is generated.
The timer interrupt source mode should be set as edge-sensitive as presented in
Table 5. No software interrupt acknowledge to the timer device is necessary.
DCS
60
level
Internal DCS bus
MMI
61
level
Main Memory Interface, i.e. the DRAM controller
Reserved
62...63
n/a
Reserved for future devices
Table 5: Interrupt Source Assignments
SOURCE NAME
SOURCE
NUMBER
INTERRUPT
OPERATING MODE
SOURCE DESCRIPTION
Table 6: TM3260 Timer Source Selection
SOURCE NAME
SOURCE NUMBER
SOURCE DESCRIPTION
TM3260 CLOCK
0
The CPU clock
PRESCALE
1
Pre-scaled CPU clock
Reserved
2
Reserved for future devices
DATABREAK
3
Data breakpoints
INSTBREAK
4
Instruction breakpoints
CACHE1
5
Cache event 1
CACHE2
6
Cache event 2
VDI_CLK1
7
VIP clock pin
VDI_CLK2
8
FGPI clock pin
VDO_CLK1
9
QVCP clock pin
VDO_CLK2
10
FGPO clock pin
AI_WS
11
AI Word Strobe pin
AO_WS
12
AO Word Strobe pin
GPIO_TIMER0
13
GPIO pin selection 0
GPIO_TIMER1
14
GPIO pin selection 1
REFERENCE_CLOCK
15
The 27 MHz input crystal clock