
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
3-6
2.4.1
DCS DRAM Aperture Control MMIO Registers
2.5 Aperture Boundaries
The MMIO aperture is always 2 Megabytes.
The DRAM aperture size range is from 1 to 256 Megabytes. Dened at boot time, it
may be changed later on by the TM3260 CPU.
The XIO aperture size range is from 1 to 128 Megabytes.
Table 1: SYSTEM Registers
Bit
Symbol
Acces
s
Value
Description
DCS DRAM Aperture Control Registers
Offset 0x06 3200
DCS_DRAM_LO
31:16
DCS_DRAM_LO
R/W
0x0000
DCS_DRAM_LO indicates the lowest DCS bus address mapped to
DRAM. Its granularity is of 64 Kilobytes.
The reset value is 0.
Writes to this register are controlled by the DCS_DRAM_WE bit in
the APERTURE_WE MMIO register.
15:0
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Offset 0x06 3204
DCS_DRAM_HI
31:16
DCS_DRAM_HI
R/W
0x0000
DCS_DRAM_HI indicates the highest DCS bus address mapped to
DRAM. Its granularity is of 64 Kilobytes.
The reset value of 0 disables memory accesses from the DCS bus.
Writes to this register are controlled by the DCS_DRAM_WE bit in
the APERTURE_WE MMIO register.
15:0
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Offset 0x06 3208
APERTURE_WE
31:1
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
0
DCS_DRAM_WE
R/W
0x0
‘0’: Writing to DCS_DRAM_LO or DCS_DRAM_HI is disabled.
‘1’: Writing to DCS_DRAM_LO or DCS_DRAM_HI is enabled.
When writing to either DCS_DRAM_LO or DCS_DRAM_HI
occurs, this bit is automatically cleared.
By default it is not authorized to write to the DCS_DRAM_LO and
DCS_DRAM_HI registers.
The address range dened by the content of DCS_DRAM_LO or
DCS_DRAM_HI must not overlap the address ranges of the
other apertures on the DCS bus. This can happen temporarily
when changing either the DCS_DRAM_LO or the
DCS_DRAM_HI. Therefore any change of the DCS_DRAM_LO
or DCS_DRAM_HI registers must be done by rst disabling the
DCS DRAM aperture. This is achieved by starting to change
DCS_DRAM_LO or DCS_DRAM_HI such that DCS_DRAM_LO
is greater than DCS_DRAM_HI.