
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
23-23
7
TxDoneInt
RO
Interrupt was triggered because a non-real-time descriptor was
transmitted and the Interrupt bit in its descriptor was set.
6
TxFinishedInt
RO
Interrupt was triggered because all non-real-time descriptors have
been processed, so that now ProduceIndex == ConsumeIndex.
5
TxErrorInt
RO
Interrupt was triggered on non-real-time transmit errors:
LateCollision, ExcessiveCollision, ExcessiveDefer, and
NoDescriptor or Underrun.
4
TxUnderrunInt
RO
Interrupt set on a fatal underrun error in the non real-time transmit
queue. The fatal interrupt should be resolved by a Tx soft-reset. The
bit is not set in case of a non fatal underrun error.
3
RxDoneInt
RO
Interrupt was triggered because a receive descriptor has been
processed and the Interrupt bit in its descriptor was set.
2
RxFinishedInt
RO
Interrupt was triggered because all receive descriptors have been
processed, so that now ProduceIndex == ConsumeIndex.
1
RxErrorInt
RO
Interrupt was triggered on receive errors: AlignmentError,
RangeError, LengthError, SymbolError, CRCError, or NoDescriptor
or Overrun.
0
RxOverrunInt
RO
Interrupt was triggered on fatal overrun error in the receive queue.
The fatal interrupt should be resolved by a Rx soft-reset. The bit is
not set in case of a non fatal underrun error.
Offset 0x07 2FE4
Interrupt Enable Register (IntEnable)
31:14
-
Unused
13
WakeupIntEn
R/W
Enable interrupts triggered by a Wakeup event detected by the
receive lter.
12
SoftIntEn
R/W
Enable interrupts triggered when software writes a 1 to the int_set
Softinterrupt register.
11
TxRtDoneIntEn
R/W
Enable interrupts triggered when a real-time descriptor has been
transmitted while the Control.Interrupt bit in the descriptor was set.
10
TxRtFinishedIntEn
R/W
Enable triggering interrupts when all real-time descriptors have
been processed, when ProduceIndex == ConsumeIndex.
9
TxRtErrorIntEn
R/W
Enable interrupts on real-time transmit errors.
8
TxRtUnderrunIntEn
R/W
Enable interrupts on real-time transmit buffer or descriptor underrun
conditions.
7
TxDoneIntEn
R/W
Enable interrupts when a non-real-time descriptor has been
transmitted and the Interrupt bit in its descriptor was set.
6
TxFinishedIntEn
R/W
Enable interrupts when all non-real-time descriptors have been
processed, when ProduceIndex == ConsumeIndex.
5
TxErrorIntEn
R/W
Enable interrupts on non-real-time transmit errors.
4
TxUnderrunIntEn
R/W
Enable interrupts on non-real-time transmit buffer or descriptor
underrun conditions.
3
RxDoneIntEn
R/W
Enable interrupts when a receive descriptor has been processed
and the Interrupt bit in its descriptor was set.
2
RxFinishedIntEn
R/W
Enable interrupts when all receive descriptors have been
processed, when ProduceIndex == ConsumeIndex.
Table 2: LAN100 Registers …Continued
Bit
Symbol
Acces
s
Value
Description