
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 1: Integrated Circuit Data
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
1-2
PNX1500 uses different I/Os depending on the type of the interface, e.g. PCI, or
electrical characteristics needed for the functionality, e.g. a clock signal requires
sharper edges than a regular signal. The following table summarizes the types of I/
Os, a.k.a. pads, used in PNX1500.
The above pad types are used in the modes listed in the following table
Unused pins may remain unconnected, i.e. oating if they contain an internal pull-up
or pull-down. More specically,
Table 1: PNX1500 I/O Types
Pad Type
Description
PCIT5V
PCI 2.2 compliant I/O using 3.3- or 5- V PCI signaling conventions.
IIC3M4SDAT5V
IIC3M4SCLT5V
Open drain 3.3- or 5- V I2C I/Os.
BPX2T14MCP
3.3-V low impedance output, with fast rise/fall time, combined with 3.3-V input only.
Used for Clock signals requires board level 27-33
series terminator resistor to match 50 PCB trace.
BPTS1CP
3.3-V regular impedance output, with fast rise/fall time, combined with 3.3-V input only.
BPTS1CHP
3.3-V regular impedance output, with fast rise/fall time, combined with 3.3-V input only with hysteresis.
BPTS3CP
3.3-V regular impedance output, with slow rise/fall time, combined with 3.3-V input only.
BPTS3CHP
3.3-V regular impedance output, with slow rise/fall time, combined with 3.3-V input only with hysteresis.
BPT3MCHT5V
3.3-V regular impedance output, with slow rise/fall time, combined with 5-V tolerant input with hysteresis.
BPT3MCHDT5V 3.3-V regular impedance output, with slow rise/fall time, combined with 5-V tolerant input with hysteresis
and internal pull-down.
Note: The pull-down is NOT strong enough to actually pull down a 5-V TTL input. Instead the TTL input
pin sees a ‘1’.
IPCP
3.3-V input only.
IPCHP
3.3-V input only with hysteresis.
SSTLCLKIO
SSTL_2 low impedance, e.g. DDR SDRAM clocks. Requires a board level 10
series terminator resistor
to match a 50
PCB trace.
SSTLADDIO
SSTL_2 low impedance for output signals, e.g. DDR SDRAM address and control signals. Requires a
board level matched 50
PCB trace.
SSTLDATIO
SSTL_2 low impedance for DDR SDRAM data signals. Requires a board level matched 50
PCB trace.
Table 2: PNX1500 I/O Modes
Modes
Description
IN
Input only, except during boundary scan or GPIO mode.
OUT
Output only, except when used as a GPIO pin.
OD
Open drain output - active pull low, no active drive high, requires external pull-up.
I/O
Input or Output.
I/OD
Input or open drain output - active pull low, no active drive high, requires external pull-up.
I/O/D
Input or output or open drain output with input - active pull low, no active drive high, requires external pull-
up when operated in open drain mode.
O
Output or oating.