- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376976 > DS3112N RECT BRIDGE GPP 15A 600V GBJ PDF資料下載
參數(shù)資料
| 型號： | DS3112N |
| 英文描述： | RECT BRIDGE GPP 15A 600V GBJ |
| 中文描述： | 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器 |
| 文件頁數(shù)： | 107/135頁 |
| 文件大小： | 585K |
| 代理商： | DS3112N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁當(dāng)前第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁
DS3112
107 of 135
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of
the DS3112 can be sampled at the Boundary Scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS3112 to shift data
into the Boundary Scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS3112. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The Boundary Scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the Boundary Scan register.
BYPASS
When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the
device's normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register's parallel output. The device ID code will always have a one in the LSB position.
The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed
by 16 bits for the device and 4 bits for the version. The device ID code for the DS3112 is
0000B143h
.
HIGH-Z
All digital outputs will be placed into a high impedance state. The Bypass Register will be connected
between JTDI and JTDO.
CLAMP
All digital outputs will output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
11.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register.
An optional test register, the Identification register, has been included in the DS3112 design. It is used in
conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGH-Z
instructions that provides a short path between JTDI and JTDO.
Identification Register
The Identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3112RD | RECT BRIDGE GPP 15A 800V GBJ |
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。